# US 7,744,006 B2 · Semiconductor device and memory card having the same

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- Number: US 7,744,006 B2
- Document ID: US7744006B2
- Status: Granted
- Kind: B2
- Application number: 12/115,418
- Filed: 2008-05-05
- Published: 2009-01-08
- Granted: 2010-06-29
- Earliest claimed: 2004-10-04
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Nobuyoshi Nara
- Web page: https://patentgrep.com/patent/US7744006B2

## CPC

- G06K 19/07: with integrated circuit chips
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS

## Abstract

A semiconductor device includes a first circuit which operates in accordance with an internal clock, a second circuit which generates information of which an external apparatus is to be notified, an interface section which notifies the external apparatus of the information generated by the second circuit without using the first circuit upon receiving a predetermined command from the external apparatus, and a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate. The information is determined depending on whether each of the plurality of terminals is electrically connected to the power terminal or ground terminal on the substrate.

## Claims

### Claim 1

A memory system applicable to a memory device having a controller which includes a plurality of connection portions and a circuit operable in accordance with an internal clock, the memory system including:
an interface unit configured to notify an external apparatus of information without using the circuit upon receiving a predetermined command from the external apparatus before the memory device enters a standby state,
wherein the information is determined depending on whether each of the plurality of connection portions is electrically connected to a power terminal or a ground terminal.

### Claim 2 (depends on 1)

The memory system according to claim 1, wherein the predetermined command is a command input before oscillation of the internal clock is completed.

### Claim 3 (depends on 1)

The memory system according to claim 1, wherein the information includes information indicating a storage capacity of a predetermined memory.

### Claim 4

A memory system applicable to a memory device having a controller which includes a plurality of connection portions and a circuit operable in accordance with an internal clock, the memory system including:
an interface unit configured to notify an external apparatus of information without using the circuit upon receiving a predetermined command from the external apparatus before the memory device enters a standby state,
wherein the information is determined depending on whether or not each of the plurality of connection portions is electrically connected to one of a plurality of terminals.

### Claim 5 (depends on 4)

The memory system according to claim 4, wherein the predetermined command is a command input before oscillation of the internal clock is completed.

### Claim 6 (depends on 4)

The memory system according to claim 4, wherein the information includes information indicating a storage capacity of a predetermined memory.

### Claim 7 (depends on 4)

The memory system according to claim 4, wherein the plurality of terminals are ground terminals, and
the device further includes:
pull-up resistors each of which is connected between a respective one of the plurality of connection portions and a power supply and which is capable of switchably enabling and disabling a pull-up operation of pulling up a signal level obtained from the respective one of the plurality of connection portions; and
a control unit configured to switchably control a pull-up resistor to enable or disable the pull-up operation depending on whether the signal level is high or low.

### Claim 8 (depends on 4)

The memory system according to claim 4, wherein the plurality of terminals are power terminals, and
the device further includes:
pull-up resistors each of which is connected between a respective one of the plurality of connection portions and a ground and which is capable of switchably enabling and disabling a pull-down operation of pulling down a signal level obtained from the respective one of the plurality of connection portions; and
a control unit configured to switchably control a pull-down resistor to enable or disable the pull-down operation depending on whether the signal level is low or high.