Adaptive cooperative scheduling
AssigneeHewlett-Packard Development Company, L.P.
InventorsScott J. Norton, Hyun J. Kim, Swapneel Kekre
Life of this patent
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Abstract
A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.
Claims18
In a computer system, a method for coordinating scheduling of threads among a plurality of processors, comprising:
- collecting, from a kernel of an operating system executing on said computer system, using a cooperative scheduling component (CSC), system data pertaining to said plurality of processors;
- calculating, using said CSC, unified scheduling-related parameters (USRPs) from said system data and thread run-time behavior data embedded in said threads;
- and
- furnishing said USRPs from said CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby said at least two of said thread launcher, said thread balancer, and said thread stealer employ said USRPs to perform their respective scheduling-related tasks.
In a computer system, an arrangement for coordinating scheduling of threads on a plurality of processors, comprising:
- at least two of a thread launcher, a thread balancer, and a thread stealer, said thread launcher being configured to launch a first thread, responsive to a first subset of unified scheduling-related parameters (USRPs) pertaining to said plurality of processors, on at least a first processor of said plurality of processors,
- said thread balancer being configured to evacuate, responsive to a second subset of said USRPs, a second thread from a second processor of said plurality of processors to a third processor of said plurality of processors, and
- said thread stealer being configured to evacuate, responsive to a third subset of said USRPs and on behalf of a fourth processor of said plurality of processors, a third thread from a fifth processor of said plurality of processors to said fourth processor;
- and
- a cooperative scheduling component (CSC) coupled to communicate with said at least two of said thread launcher, said thread balancer, and said thread stealer, said CSC being configured to provide said USRPs for use by said at least two of said thread launcher, said thread balancer, and said thread stealer.
A computer-readable medium having computer readable code embodied therein, said computer readable code being configured to coordinate scheduling of threads among a plurality of processors, comprising:
- computer readable code for collecting, from a kernel of an operating system executing on said computer system, using a cooperative scheduling component (CSC), system data pertaining to said plurality of processors;
- computer readable code for calculating, using said CSC, unified scheduling-related parameters (USRPs) from said system data and thread run-time behavior data embedded in said threads;
- and
- computer readable code for furnishing said USRPs from said CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby said at least two of said thread launcher, said thread balancer, and said thread stealer employ said USRPs to perform their respective scheduling-related tasks.
Dependencies are inferred from the claim text.