Optimizing integrated circuit design through use of sequential timing information

A method to determine a measure of sequential flexibility in a circuit design comprising:

• determining a limit upon clock cycle duration indicative of a highest proportion of delay to number of registers from among a plurality of structural cycles in the design;
• and
• using a computer to determine for a register in the circuit design, a maximal limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, wherein the maximal limit is substantially equal to a minimal addition of delay selected from among maximal limits of additional delay that can be added to individual structural cycles in which the circuit element is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

A system to determine a measure of sequential flexibility in a circuit design comprising:

• means for obtaining a value for a limit upon clock cycle duration;
• and
• means for determining for a register in the circuit design, a limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, which is not greater than any of respective maximal delays that can be added to respective structural cycles in which the register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

An article of manufacture that includes a computer data storage device, encoded with code structure, when executed by a computer causes the computer data storage device to implement a method, comprising:

• obtaining a value for a limit upon clock cycle duration;
• and
• using a computer to determine for a register in the circuit design, a limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, which is not greater than any of respective maximal delays that can be added to respective structural cycles in which the register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.