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US 7,743,311 B2Granted
Combined encoder/syndrome generator with reduced delay
AssigneeHitachi Global Storage Technologies Netherlands B.V.
InventorsMartin Hassner, Kirk Hwang
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Abstract
A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.
Claims8
A combined encoder/syndrome generator circuit comprising:
- a first adder chain circuit block coupled to receive an input sequence, the first adder chain circuit block comprising first adder stages that generate syndromes during a decoding mode;
- a second adder chain circuit block coupled to receive the input sequence, the second adder chain circuit block comprising second adder stages that generate syndromes during the decoding mode,
- wherein the first and the second adder chain circuit blocks generate separate outputs in parallel that are used to generate check symbols during an encoding mode, and a current output of the second adder chain circuit block is dependent on a previous output of the first adder chain circuit block;
- and
- a first adder coupled to the outputs of the first and the second adder chain circuit blocks, wherein the first adder adds the generated syndromes from the first and the second adder stages.
2 more elements
A combined encoder/syndrome generator circuit comprising:
- a first adder chain circuit block coupled to receive an input sequence, the first adder chain circuit block comprising first adder stages that generate syndromes during a decoding mode;
- a second adder chain circuit block coupled to receive the input sequence, the second adder chain circuit block comprising second adder stages that generate syndromes during the decoding mode,
- wherein the first and the second adder chain circuit blocks generate separate outputs in parallel that are used to generate check symbols during an encoding mode, and a current output of the second adder chain circuit block is dependent on a previous output of the first adder chain circuit block;
- a first register for storing outputs of the first adder chain circuit block;
- a first adder that adds contents of the first register and the input sequence;
- a third adder chain circuit block coupled to receive an output of the first adder, the third adder chain circuit block comprising third adder stages that generate syndromes during the decoding mode, wherein the first, the second, and the third adder chain circuit blocks generate separate outputs in parallel during the encoding mode;
- a second register for storing outputs of the third adder chain circuit block;
- a second adder that adds contents of the second register and the output of the first adder;
- and
- a fourth adder chain circuit block coupled to receive an output of the second adder, the fourth adder chain circuit block comprising fourth adder stages that generate syndromes during the decoding mode, wherein the first, the second, the third, and the fourth adder chain circuit blocks generate separate outputs in parallel during the encoding mode.
7 more elements
Dependencies are inferred from the claim text.