Back to results
US 7,743,306 B2Granted
Test vector generating method and test vector generating program of semiconductor logic circuit device
AssigneeKyushu Institute of Technology
InventorsXiaoqing Wen, Seiji Kajihara
Life of this patent
Estimating the term…
Abstract
The X-type of each bit permutation is determined (step 301). When there are X-types except for X-type 1, i.e., X-type with no don't-care bits, total capture state transition numbers TECTA1 and TECTA2 for capture clock pulses C1 and C2 are calculated (step 303). As a result, when TECTA1>TECTA2, an X-type is selected for the capture clock pulse C1 and a first X-filling processing is performed (see step 305). On the other hand, when TECTA1≦TECTA2, an X-type is selected for the capture clock pulse C2 and a second X-filling processing is performed (step 306).
Claims16
A test vector generating method of a semiconductor logic circuit device comprising:
- a combinational portion (11) having external input lines (PI), pseudo external input lines (PPI), external output lines (PO) and pseudo external output lines (PPO);
- and
- a scan flip-flop group (12) connected between said pseudo external output lines and said pseudo external input lines,
- characterized in that said combinational portion is hypothetically formed by first and second combinational portions (111, 112) having said external input lines in common, said scan flip-flop group being hypothetically formed by first and second scan flip-flop groups (121, 122) operated by first and second capture clock pulses (C1, C2) continuously performed upon said first and second combinational portions,
- said test vector generating method comprising:
- a first filling step adapted to fill 0 or 1 in don't-care bits of a test cube so that the same logic value may appear in a bit of the pseudo external input lines and a respective bit of the pseudo external output lines of said first combinational portion, when a test cube including don't-care bits not used for detecting faults is given to the external input lines and the pseudo external input lines of said first combinational portion and there is an don't-care bit in said bit of the pseudo external input lines of said first combinational portion or said respective bit of the pseudo external output lines of said first combinational portion;
- a second filling step adapted to fill 0 or 1 in don't-care bits of a test cube so that the same logic value may appear in a bit of the pseudo external input lines and a respective bit of the pseudo external output lines of said second combinational portion, when a test cube including don't-care bits not used for detecting faults is given to the external input lines and the pseudo external input lines of said first combinational portion and there is an don't-care bit in said bit of the pseudo external input lines of said second combinational portion or said respective bit of the pseudo external output lines of said second combinational portion;
- a balancedly discrepancy decreasing step adapted to select said first and second filling steps and repeatedly operate the selected filling step so that the number of discrepancies between bits of the pseudo external input lines of said first combinational portion and respective bits of the pseudo external output lines of said first combinational portion and the number of discrepancies between bits of the pseudo external input lines of said second combinational portion and respective bits of the pseudo external output lines of said second combinational portion are decreased in a balanced manner;
- and
- a third filling step adapted to fill 0 or 1 in all specified bits of the external input lines of said first combinational portion, when there is no don't-care bit in the pseudo external input lines of said first combinational portion, the pseudo external output lines of said first combinational portion and the pseudo external output lines of said second combinational portion,
- thereby converting said test cube into a test vector having no don't-care bits.
8 more elements
A test vector generating program of a semiconductor logic circuit device comprising:
- a combinational portion (11) having external input lines (PI), pseudo external input lines (PPI), external output lines (PO) and pseudo external output lines (PPO);
- and
- a scan flip-flop group (12) connected between said pseudo external output lines and said pseudo external input lines,
- characterized in that said combinational portion is hypothetically formed by first and second combinational portions (111, 112) having said external input lines in common, said scan flip-flop group being hypothetically formed by first and second scan flip-flop groups (121, 122) operated by first and second capture clock pulses (C1, C2) continuously performed upon said first and second combinational portions,
- said test vector generating program comprising:
- a first filling processing adapted to fill 0 or 1 in don't-care bits of a test cube so that the same logic value may appear in a bit of the pseudo external input lines and a respective bit of the pseudo external output lines of said first combinational portion, when a test cube including don't-care bits not used for detecting faults is given to the external input lines and the pseudo external input lines of said first combinational portion and there is an don't-care bit in said bit of the pseudo external input lines of said first combinational portion or said respective bit of the pseudo external output lines of said first combinational portion;
- a second filling processing adapted to fill 0 or 1 in don't-care bits of a test cube so that the same logic value may appear in a bit of the pseudo external input lines and a respective bit of the pseudo external output lines of said second combinational portion, when a test cube including don't-care bits not used for detecting faults is given to the external input lines and the pseudo external input lines of said first combinational portion and there is an don't-care bit in said bit of the pseudo external input lines of said second combinational portion or said respective bit of the pseudo external output lines of said second combinational portion;
- a balancedly discrepancy decreasing processing adapted to select said first and second filling steps and repeatedly operate the selected filling step so that the number of discrepancies between bits of the pseudo external input lines of said first combinational portion and respective bits of the pseudo external output lines of said first combinational portion and the number of discrepancies between bits of the pseudo external input lines of said second combinational portion and respective bits of the pseudo external output lines of said second combinational portion are decreased in a balanced manner;
- and
- a third filling processing adapted to fill 0 or 1 in all specified bits of the external input lines of said first combinational portion, when there is no don't-care bit in the pseudo external input lines of said first combinational portion, the pseudo external output lines of said first combinational portion and the pseudo external output lines of said second combinational portion,
- thereby converting said test cube into a test vector having no don't-care bits.
8 more elements
Dependencies are inferred from the claim text.