Compressing test responses using a compactor
OwnerJanusz Rajski, Jerzy Tyszer +3inventors
InventorsJanusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
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Abstract
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
Claims30
An apparatus for compressing test responses in an integrated circuit, comprising:
- a plurality of memory elements;
- and
- an injector network comprising combinational logic, the injector network having injector-network outputs and injector-network inputs,
- each injector-network output being coupled to a respective one of the memory elements,
- each injector-network input being logically coupled to two or more injector-network outputs according to a respective injector polynomial, the respective injector polynomial being selected to prevent one, two, and odd-numbered error masking in the memory elements.
A computer-readable medium storing computer-executable instructions for causing a computer system to design an apparatus, the apparatus comprising:
- a plurality of memory elements;
- and
- an injector network comprising combinational logic, the injector network having injector-network outputs and injector-network inputs,
- each injector-network output being coupled to a respective one of the memory elements,
- each injector-network input being logically coupled to two or more injector-network outputs according to a respective injector polynomial, the respective injector polynomial being selected to prevent one, two, and odd-numbered error masking in the memory elements.
A computer-readable medium storing a design database that includes design information for an apparatus, the apparatus comprising:
- a plurality of memory elements;
- and
- an injector network comprising combinational logic, the injector network having injector-network outputs and injector-network inputs,
- each injector-network output being coupled to a respective one of the memory elements,
- each injector-network input being logically coupled to two or more injector-network outputs according to a respective injector polynomial, the respective injector polynomial being selected to prevent one, two, and odd-numbered error masking in the memory elements.
Dependencies are inferred from the claim text.