Integrated circuit test using clock signal modification

An integrated circuit comprising:

• a test signal generator that receives a clock signal including pulses having leading edges and trailing edges that occur at predetermined intervals and that selectively generates a modified clock signal by adjusting timing of at least one of the leading and trailing edges of at least one of the pulses;
• a signal path that includes a circuit and that receives one of the clock signal and the modified clock signal from the test signal generator;
• a measurement circuit that receives first and second outputs of the signal path generated during the clock signal and the modified clock signal, respectively;
• a comparing circuit that compares the first and second outputs;
• and
• an analysis circuit that selectively identifies the signal path as flawed based on the comparison.

An integrated circuit comprising:

• a test signal generator that receives a clock signal and that outputs one of the clock signal and a modified clock signal,
• wherein the test signal generator generates the modified clock signal based on a control signal, the clock signal and a delayed clock signal, and
• wherein the modified clock signal has a pulse rate that is the same as the clock signal and at least one pulse of the modified clock signal has a pulse duration that is shorter than a pulse duration of pulses of the clock signal;
• at least one signal path including a circuit that receives one of the clock signal and the modified clock signal from the test signal generator;
• and
• an analysis circuit that selectively identifies the signal path as flawed based on the at least one pulse.

An integrated circuit comprising:

• a test signal generator that receives a clock signal and that outputs one of the clock signal and a modified clock signal,
• wherein the test signal generator generates the modified clock signal based on a control signal, the clock signal and a delayed clock signal, and
• wherein the modified clock signal has a pulse rate that is the same as the clock signal and at least one pulse of the modified clock signal has a pulse duration that is shorter than a pulse duration of pulses of the clock signal;
• at least one signal path including a circuit that receives one of the clock signal and the modified clock signal from the test signal generator;
• a measurement circuit that receives first and second outputs of the signal path based on the clock signal and the modified clock signal, respectively;
• a comparing circuit that compares the first and second outputs;
• and
• an analysis circuit that selectively identifies the signal path as flawed based on the comparison.

An integrated circuit comprising:

• a test signal generator that receives a clock signal including pulses having leading edges and trailing edges that occur at predetermined intervals and that selectively modifies the clock signal to adjust timing of at least one of the leading and trailing edges of at least one of the pulses;
• a signal path that includes a circuit and that receives the clock signal from the test signal generator;
• and
• an analysis circuit that selectively identifies the signal path as flawed based on the adjusted timing.