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US 7,743,298 B1Granted
Methods and apparatus for scan testing of integrated circuits with scan registers
AssigneeCadence Design Systems, Inc.
InventorsSandeep Bhatia, Oriol Roig
Life of this patent
Estimating the term…
Abstract
In one embodiment of the invention, a method of scan testing an integrated circuit is disclosed. The method includes scanning a first test vector and a second test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch, a scan latch, and a functional latch; and applying the first and the second test vectors sequentially in a delay fault test via the plurality of scan registers to a combinational logic circuit coupled to the plurality of scan registers.
Claims9
A method comprising:
- scanning a first test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including
- a master latch to store data,
- a scan latch and a functional latch having inputs coupled together to an output of the master latch,
- the scan latch to receive and to store the data from the master latch in response to enabling a scan mode, and
- the functional latch to receive and to store the data from the master latch in response to disabling the scan mode;
- wherein the scanning of the first test vector sequentially into the plurality of scan registers includes
- enabling the scan mode to scan the first test vector into the plurality of scan registers;
- and
- applying the first test vector via the plurality of scan registers to a combinational logic circuit coupled to the functional latch of one or more of the plurality of scan registers,
- wherein the applying of the first test vector to the combinational logic circuit includes
- disabling the scan mode to update an output of the functional latch of each of the plurality of scan registers with the first test vector.
8 more elements
An integrated circuit comprising:
- a combinational logic circuit;
- a plurality of scan registers coupled serially together, each of the plurality of scan registers including
- a master latch to receive and store data,
- a functional latch and a scan latch having inputs coupled together to an output of the master latch,
- the functional latch coupled to the combinational logic circuit, and
- the scan latch coupled to a master latch of a next scan register to pass scan data while the functional latch holds functional data substantially steady in a scan mode;
- an input pin configured to couple to a tester to receive a plurality of test vectors wherein the test vectors are scanned into the plurality of scan registers sequentially and then applied to the combinational logic circuit via the functional latch of each of the plurality of scan registers;
- and
- an output pin configured to couple to the tester to output a state of the combinational logic circuit captured by the plurality of scan registers in response to the plurality of test vectors wherein the state of the combinational logic circuit captured by the plurality of scan registers is held in the scan latch of each of the plurality of scan registers.
6 more elements
Dependencies are inferred from the claim text.