Logic analyzer systems and methods for programmable logic devices

A system comprising:

• a programmable logic device (PLD);
• means for entering trigger unit information directed to internal PLD signals to provide trigger unit output signals based on the internal PLD signals for the corresponding trigger units;
• means for entering trigger expression information as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals;
• means for generating configuration data based on the trigger unit information and the trigger expression information, wherein the configuration data for a trigger expression of the trigger expression information configures a memory of the PLD;
• means for providing the configuration data to the PLD, wherein the trigger expression is stored within the memory of the PLD;
• and
• means for routing the trigger unit output signals to the memory as address signals for the trigger expression.

A programmable logic device comprising:

• a plurality of trigger unit circuits of a logic analyzer, the trigger unit circuits adapted to provide trigger unit output signals based on internal PLD signals;
• memory;
• and
• a trigger expression circuit responsive to a text string of logic operators and operands representing a trigger expression of the logic analyzer, wherein the operands represent trigger unit output signals, the trigger expression circuit adapted to program the memory with a truth table based on the text string, with the trigger unit output signals to be provided to the programmed memory as address signals.