System and method for testing an integrated circuit
AssigneeInfineon Technologies AG
InventorsAlbrecht Mayer, Klaus Scheibert, Harry Siebert
Life of this patent
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Abstract
A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface, wherein the volatile memory area is connected to the interface to be written thereto by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.
Claims22
A system for testing an integrated circuit comprising:
- at least one central processing unit;
- at least one volatile memory area and at least one non-volatile memory area;
- an interface;
- and
- a test device coupled with the integrated circuit, the central processing unit accessing the non-volatile memory area in a normal operation mode, and wherein in a test operation mode the test device is configured to stop program execution, write data in the volatile memory area via the interface, and start program execution, the central processing unit accessing the volatile memory area in the test operation mode.
A method for testing an integrated circuit comprising:
- defining the integrated circuit to include at least one central processing unit, a volatile memory area connected therewith, a non-volatile memory area, and an interface connected with the volatile memory area, the central processing unit accessing the non-volatile memory area in a normal operation mode, the method further comprising, in a test operation mode;
- stopping a program execution;
- writing data in the volatile memory area via the interface;
- and
- starting the program execution, the central processing unit accessing the volatile memory area in the test operation mode.
Dependencies are inferred from the claim text.