Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit

A design apparatus of a semiconductor integrated circuit including a storage circuit or an information holding circuit composed of a transistor, comprising:

• a first mathematical expression deriving unit to derive a first mathematical expression indicating a dependence of a soft error rate on an information storage node diffusion layer area at the same information storage node voltage from a measurement result of a relationship between a soft error rate and the information storage node diffusion layer area of the storage circuit or the information holding circuit with use of a plurality of information storage node voltages as a parameter;
• a second mathematical expression deriving unit to derive a second mathematical expression indicating a soft error rate as a function of the information storage node diffusion layer area and the information storage node voltage by substituting a relationship indicating a dependence of a soft error rate on the information storage node voltage at the same information storage node diffusion layer area into the first mathematical expression;
• and
• a SER calculation unit to calculate a soft error rate by substituting a desired information storage node diffusion layer area and a desired information storage node voltage into the second mathematical expression.

A static random memory (SRAM) device comprising;

• a plurality of cells;
• and
• a peripheral circuit;
• wherein an area of one storage node diffusion layer of the cells is smaller than about 0.04 μm2, and
• wherein a selected cell of the cells receives a power supply voltage higher than that of a non-selected cell of the cells and the power supply voltage is as the same as a power supply voltage for the peripheral circuit.