Built-in at-speed bit error ratio tester
AssigneeAltera Corporation
InventorShoujun Wang
Life of this patent
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Abstract
A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.
Claims24
An integrated circuit device on which is implemented a bit error ratio tester that tests the bit error ratio of a device under test (DUT), comprising:
- a variable delay line that receives as input a first clock signal and is operative to variably phase-delay the first clock signal to produce a second clock signal having phase that steps, in time, across a data eye of a data signal containing jitter from the DUT;
- transmitter circuitry that receives as input the first clock signal and is operative to generate and transmit pseudo-random binary sequence (PRBS) data, synchronized with the first signal, to the DUT;
- and
- receiver circuitry that receives as input the data signal from the DUT and the second clock signal, and is operative to use the second clock signal to recover the PRBS data from the data signal and to determine, for each of the steps in the phase of the second clock signal, a bit error ratio of the recovered PRBS data, wherein the receiver circuitry comprises:
- circuitry that outputs a first control signal based on a frequency associated with the second clock signal,
- circuitry that outputs a second control signal based on the data signal, and
- selection circuitry that selects as output one of the first and second control signals based on the frequency associated with the second clock signal.
An integrated circuit device on which is implemented a bit error ratio tester that tests the bit error ratio of a device under test (DUT), comprising:
- first circuitry operative to generate and transmit test data to the DUT;
- second circuitry operative to receive a data signal containing jitter from the DUT and to recover the test data from the data signal using a clock signal derived from a system clock and having phase that steps, in time, across a data eye of the data signal, wherein the second circuitry comprises:
- circuitry that outputs a first control signal based on a frequency associated with the clock signal,
- circuitry that outputs a second control signal based on the data signal,
- selection circuitry that selects as output one of the first and second control signals based on the frequency associated with the clock signal;
- and
- third circuitry operative to determine, for each of the steps in the phase of the clock signal, a bit error ratio of the recovered test data.
A method for implementing a bit error ratio tester on an integrated circuit device that tests the bit error ratio of a device under test (DUT), comprising:
- generating pseudo-random binary sequence (PRBS) data in a PRBS generator;
- transmitting the PRBS data to the DUT;
- receiving a data signal containing jitter and having embedded therein the PRBS data from the DUT;
- generating from a system clock a clock signal having phase that steps, in time, across a data eye of the data signal;
- generating a first control signal based on a frequency associated with the clock signal,
- generating a second control signal based on the data signal, and
- selecting as output one of the first and second control signals based on the frequency associated with the clock signal;
- recovering the PRBS data from the data signal based on each of the steps in the phase of the clock signal;
- and
- calculating, for each of the steps in the phase of the clock signal, a bit error ratio for the recovered PRBS data in a bit error ratio (BER) checker.
Dependencies are inferred from the claim text.