US 7,743,285 B1 · Chip multiprocessor with configurable fault isolation

Abstract

One embodiment relates to a high-availability computation apparatus including a chip multiprocessor. Multiple fault zones are configurable in the chip multiprocessor, each fault zone being logically independent from other fault zones. Comparison circuitry is configured to compare outputs from redundant processes run in parallel on the multiple fault zones. Another embodiment relates to a method of operating a high-availability system using a chip multiprocessor. A redundant computation is performed in parallel on multiple fault zones of the chip multiprocessor and outputs from the multiple fault zones are compared. When a miscompare is detected, an error recovery process is performed. Other embodiments, aspects and features are also disclosed.

Claims23

Dependent claims

A chip multiprocessor comprising:

a plurality of processor cores for executing instructions;
a plurality of memory controllers for communicating with main memory;
a plurality of input/output interfaces for receiving and transmitting data;
and
a communication system including a ring interconnect configured to interconnect the processor cores to the memory controllers and the input/output interfaces,
wherein the communication system further includes at least one ring configuration unit configured to partition the ring interconnect into multiple fault zones, each fault zone being logically isolated from other fault zones.

3 more elements

Dependencies are inferred from the claim text.

Chip multiprocessor with configurable fault isolation

Life of this patent

Chip multiprocessor with configurable fault isolation

Life of this patent

Abstract

Claims23