Assigning clock arrival time for noise reduction
AssigneeInternational Business Machines Corporation
InventorsIgor Arsovski, Joseph A. Iadanza, Jason M. Norman, Sebastian T. Ventrone
Life of this patent
Estimating the term…
Abstract
A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
Claims14
A method of reducing clock noise generated by clock signals in an integrated circuit (IC), the method comprising:
- determining a desired clock arrival time distribution of clock signals for clocked elements of the IC;
- determining a noise generating capacity of a clocked element;
- and
- re-assigning clock signal arrival times for the clocked elements based on the desired clock arrival time distribution to reduce clock noise generated by active edges of the clock signals, wherein the re-assigning is performed on a priority clocked element before a clocked element without priority, the priority clocked element having a noise generating capacity that meets a pre-set threshold.
A system of reducing clock noise generated by clock signals in an integrated circuit (IC), the system comprising:
- means for determining a desired clock arrival time distribution of clock signals for clocked elements of the IC;
- means for determining a noise generating capacity of a clocked element;
- and
- means for re-assigning clock signal arrival times for the clocked elements based on the desired clock arrival time distribution to reduce clock noise generated by active edges of the clock signals, wherein the re-assigning means re-assigns a clock arrival time for a priority clocked element before re-assigning a clock arrival time for a clocked element without priority, the priority clocked element having a noise generating capacity that meets a pre-set threshold.
A computer program product stored in a computer-readable medium for reducing clock noise generated by clock signals in an integrated circuit (IC), the computer program product comprising:
- computer usable program code, which when executed, enables a computer infrastructure to:
- determine a desired clock arrival time distribution of clock signals for clocked elements of the IC;
- enable a computer infrastructure to determine a noise generating capacity of a clocked element;
- re-assign clock signal arrival times for the clocked elements based on the desired clock arrival time distribution to reduce clock noise generated by active edges of the clock signals:
- and
- enable a computer infrastructure to re-assign a clock arrival time for a priority clocked element before re-assigning a clock arrival time for a clocked element without priority, the priority clocked element having a noise generating capacity that meets a pre-set threshold.
Dependencies are inferred from the claim text.