Security processor with bus configuration
AssigneeNXP B.V.
InventorThorwald Rabeler
Life of this patent
Estimating the term…
Abstract
A security subsystem controls the data transfer rights among components of a secured system via a common bus. The security subsystem includes a secure block that is coupled to an access controller, preferably via a hard-wired connection to the controller. This secure block exclusively controls the access rights among components, and can effectively isolate security functions and data from the main processor. Because the security is provided via access control to components or subsets of components via a common bus, an efficient and effective integration of the security subsystem within the secured system can be achieved.
Claims7
A system comprising:
- a main processor that is configured to effect a primary function of the system,
- a plurality of components that are configured to transfer data via a bus that is common to the main processor,
- an access controller that is configured to selectively inhibit data transfers between the main processor and one or more components of the plurality of components, based on defined access rights, and
- a secure block that is independent of the main processor and is configured to define the access rights;
- wherein,
- the access controller is configured to selectively inhibit the data transfers based on contents of an access control matrix whose contents define the access rights between the main processor and the one or more components, and
- the secure block is configured to exclusively control the contents of the access control matrix, and
- the access control matrix includes a definition of access rights to the access control matrix that exclusively limit a right to modify the contents of the access control matrix to the secure block.
Dependencies are inferred from the claim text.