Processor having a dedicated hash unit integrated within
AssigneeIntel Corporation
InventorsGilbert Wolrich, Matthew Adiletta, William R. Wheeler
Life of this patent
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Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
Claims7
A processor comprising:
- an instruction store to store instructions of a program to execute;
- logic circuitry to perform operations in response to the instructions of the program, the logic circuitry comprising:
- an Arithmetic Logic Unit (ALU) integrated within the processor to perform arithmetic operations in response to instructions in the program;
- and
- a dedicated hash unit integrated within the processor, the dedicated hash unit responsive to a hash request issued in response to one or more instructions of the program, to:
- access data to hash;
- perform at least one hash operation on the accessed data to hash;
- and
- output hashed data;
- the dedicated hash unit configured to concurrently perform in parallel the hash operation with concurrent performance of an arithmetic operation by the ALU,
- wherein the processor comprises multiple programmable processing units to execute program instructions in parallel, each of the programmable processing units having an associated programmable processing unit Arithmetic Logic Unit;
- and
- wherein the dedicated hash unit comprises a dedicated hash unit communicatively coupled to each of the multiple programmable processing units by a bus;
- wherein each of the multiple programmable processing units includes registers;
- wherein the accessed data to hash includes hash keys fetched from the registers of one of the multiple programmable processing units in response to the hash request, the hash request issued from the one of the multiple programmable processing units;
- wherein the dedicated hash unit comprises logic circuitry to fetch hash keys;
- wherein the Arithmetic Logic Unit integrated within the processor to perform arithmetic operations in response to instructions in the program is a one of the associated programmable processing units' Arithmetic Logic Unit;
- wherein the multiple programmable processing units issue hash requests to the dedicated hash unit;
- and
- wherein the Arithmetic Logic Unit of the programmable processing unit of a programmable processing unit that issues a hash request concurrently performs, in parallel with the hash operation, an arithmetic operation by the ALU;
- and
- wherein the dedicated hash unit comprises a dedicated hash unit shared by each of the multiple programmable processing units via the bus.
Dependencies are inferred from the claim text.