External memory controller node
AssigneeQST Holdings, LLC
InventorsFrederick Curtis Furtek, Paul L. Master
Life of this patent
Estimating the term…
Abstract
A computing machine and system to provide multiple independent simultaneous memory requests is disclosed. The computing machine includes a memory. A plurality of heterogeneous computational nodes embodied in an integrated circuit are configured to make requests for memory accesses to the memory. A memory controller allows multiple independent simultaneous requests for memory accesses by the heterogeneous computational nodes to the memory.
Claims44
A computing machine comprising:
- a memory;
- a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory;
- and
- a memory controller embodied in the integrated circuit that allows multiple independent simultaneous requests for memory accesses by the heterogeneous computational nodes to the memory.
A computing machine embodied in an integrated circuit, the computing machine in communication with an external memory device, the integrated circuit comprising:
- a plurality of heterogeneous computational nodes configured to make requests for data transfer to the external memory device;
- and
- a controller that allows multiple independent simultaneous requests for data transfer by the heterogeneous computational nodes to the external memory device.
An adaptive computing machine comprising:
- a memory;
- a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory;
- a programmable interconnection network embodied in the integrated circuit providing programmable interconnections among the heterogeneous computational nodes;
- and
- a memory controller embodied in the integrated circuit that allows multiple independent simultaneous requests for memory accesses by the heterogeneous computational nodes to the memory in response to the memory requests.
An adaptive computing machine embodied in an integrated circuit and in communication with an external memory device, the adaptive computing machine comprising:
- a plurality of heterogeneous computational nodes configured to make memory requests for data transfer to the external memory device;
- a programmable interconnection network to provide programmable interconnections among the heterogeneous computational nodes;
- and
- a controller that allows multiple independent simultaneous requests for data transfer by the heterogeneous computational nodes to the external memory device.
Dependencies are inferred from the claim text.