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AssigneeFujitsu Limited
InventorsTomoyuki Okawa, Hiroyuki Kojima, Hideki Sakata, Masaki Ukai
Estimating the term…
A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.
A cache-memory control apparatus that controls a first cache and a second cache having a cache line that is divided into a plurality of sub-lines each for storing data from the first cache, the cache-memory control apparatus comprising:
A cache-memory control method for controlling a first cache and a second cache having a cache line that is divided into a plurality of sub-lines each for storing data from the first cache, the cache-memory control method comprising:
A computer-readable recording medium that stores therein a computer program for controlling a first cache and a second cache having a cache line that is divided into a plurality of sub-lines each for storing data from the first cache, the computer program causing a computer to execute:
Dependencies are inferred from the claim text.