Interrupt mailbox in host memory

One or more computer-readable storage media comprising executable instructions that, when executed, direct a processor core of a computing device to define an interrupt database in dynamic random access memory (DRAM) of the computing device to store data for processing associated with at least one interrupt for at least one component device connected to the processor core;

• receive an indication of an interrupt generated by the component device;
• and
• responsive to the indication:
• access corresponding data for processing from the interrupt database to process the interrupt, wherein the data for processing is written by the component device to interrupt database;
• and
• communicate status messages and a command to the at least one component device connected to the processor core, wherein the command is selected from a group comprising:
• wait;
• reinitialize;
• busy;
• error indication;
• or
• resend.

A system comprising:

• an interconnect to connect a plurality of devices to a host;
• a host dynamic random access memory (DRAM);
• and
• a plurality of interrupt mailboxes defined in the host DRAM to store data for processing, wherein each interrupt mailbox corresponds to a single device, and the data being associated with an interrupt received via the interconnect from a particular device;
• and
• an interrupt controller to:
• receive an interrupt message communicated by the particular device to alert the host to the interrupt;
• and
• responsive to the interrupt message:
• cause execution of the module to process the interrupt via the associated data for processing stored in the interrupt mailbox;
• and
• cause communication of status messages and a command to the particular device, wherein the command is selected from a group comprising:
• wait;
• reinitialize;
• busy;
• error indication;
• or
• resend.