Logic gateway circuit for bus that supports multiple interrupt request signals

A logic gateway circuit for a bus of a computer system, the bus supporting a plurality of interrupt request signals generated from a plurality of target devices connected to the bus, the logic gateway circuit comprising:

• an output OR gate having a plurality of input terminals and an interrupt request signal output terminal;
• and
• a plurality of gateway circuits respectively connected between the interrupt request signal output terminal of the output OR gate and the target devices, each gateway circuit having an interrupt request signal input terminal electrically connected to one of the target devices for receiving the interrupt request signal generated by the target device and generating a gateway signal according to a signal state of the interrupt request signal output terminal of the output OR gate and a signal state of the interrupt request signal of the target device so as to allow the interrupt request signal of the target device to transmit through the gateway circuit to the output OR gate or to selectively queue the interrupt request signal in the gateway circuit;
• wherein said logic gateway circuit being devoid of any processing software.