Quality of service (QoS) processing of data packets

A method for providing Quality of Service (QoS) processing of a plurality of data packets, the method comprising:

• storing the plurality of data packets received by a processing engine in a first memory;
• storing a plurality of interrupt masks in consecutive locations of a second memory starting from a base address, each interrupt mask comprising a bit pattern specifying whether an interrupt is masked for a queue of the plurality of queues;
• storing an interrupt mask address pointer in a third memory;
• reading, by a processor, an interrupt status register to determine which queue of a plurality of queues is causing an interrupt, the queue comprising address of at least one data packet of the plurality of data packets;
• reading, by said processor, the interrupt mask from said plurality of interrupt masks using said interrupt mask address pointer stored in said third memory;
• performing a logical operation at said processor between the contents of the interrupt status register and an interrupt mask of a plurality of interrupt masks stored in said second memory;
• processing the plurality of data packets based on the logical operation at said processor;
• and
• incrementing said interrupt mask address pointer stored in said third memory to point to another interrupt mask of the plurality of interrupt masks.

An article comprising a storage medium having stored thereon instructions that when executed by a machine result in the following:

• storing a plurality of data packets received by a processing engine in a first memory;
• storing a plurality of interrupt masks in consecutive locations of a second memory starting from a base address, each interrupt mask comprising a bit pattern specifying whether an interrupt is masked for a queue of the plurality of queues;
• storing an interrupt mask address pointer in a third memory;
• reading, by a processor, an interrupt status register to determine which queue of a plurality of queues is causing an interrupt, the queue comprising address of at least one data packet of the plurality of data packets;
• reading, by said processor, the interrupt mask from said plurality of interrupt masks using said interrupt mask address pointer stored in said third memory;
• performing a logical operation by said processor between the contents of the interrupt status register and an interrupt mask of a plurality of interrupt masks stored in said second memory;
• processing the plurality of data packets based on the logical operation at said processor;
• and
• incrementing said interrupt mask address pointer stored in said third memory, thereby pointing to another interrupt mask of the plurality of interrupt masks.

A system for providing Quality of Service (QoS) processing of a plurality of data packets, the system comprising:

• a processing engine capable of receiving the plurality of data packets;
• a first memory for storing the plurality of data packets received by the processing engine;
• a queue manager module comprising:
• an interrupt status register, and
• a plurality of queues comprising an address of at least one data packet of the plurality of data packets, wherein individual bits in the interrupt status register specifies a queue of the plurality of queues causing an interrupt;
• a second memory for storing a plurality of interrupt masks in consecutive locations starting from a base address, each interrupt mask comprising a bit pattern specifying whether an interrupt is masked for a queue of the plurality of queues;
• a third memory for storing an interrupt mask address pointer;
• at least one processor configured to:
• read the interrupt status register to determine which queue of the plurality of queues is causing an interrupt,
• read an interrupt mask from said plurality of interrupt masks using said interrupt mask address pointer stored in said third memory;
• perform a logical operation between the contents of the interrupt status register and said plurality of interrupt masks stored in said second memory;
• and
• process the plurality of data packets based on said logical operation;
• and
• a priority register in the network processing engine for storing information embedded inside the plurality of data packets.