Method and apparatus for communication between a processor and hardware blocks in a programmable logic device

A method of communication between a plurality of hardware blocks configured in an integrated circuit and a computation device external to the integrated circuit, comprising:

• receiving words from the computation device into a first-in-first-out buffer (FIFO) in the integrated circuit;
• decoding an address component of a word at the top of the FIFO to select a memory location in a respective memory space associated with one of the hardware blocks;
• storing a data component of the word to the selected memory location in the respective memory space associated with the one of the hardware blocks;
• after the storing of the data component of the word in the respective memory space associated with the one of the hardware blocks, asserting a respective write-ready signal by the one of the hardware blocks;
• selecting, in response to the decoded address component, the respective write-ready signal asserted by the one of the hardware blocks from a plurality of write-ready signals from the plurality of hardware blocks;
• and
• popping a top word from the FIFO in response to the selected write-ready signal asserted by the one of the hardware blocks.

A processing system, comprising:

• a computation device having a processor and a memory coupled to a system bus;
• and
• an integrated circuit configured to include an interface and a processing engine having respective memory spaces associated with a plurality of hardware blocks, the interface including:
• a bus controller for receiving words from the system bus of the computation device;
• a first-in-first-out buffer (FIFO) in communication with the bus controller for storing the words;
• an address decoder for decoding an address component of each of the words to obtain addresses of memory locations in the memory space;
• a multiplexer having a control port coupled to the address decoder, input ports respectively coupled to the hardware blocks for receiving write-ready signals, and an output port coupled to a pop control terminal of the FIFO;
• and
• a strobe generator for providing a strobe signal to the processing engine, the strobe signal configured to store the words in the respective memory locations;
• and
• wherein after a word is stored in the respective memory space associated with an addressed one of the hardware blocks, the addressed one of the hardware blocks asserts a respective write-ready signal to the multiplexer, in response to a control signal from the address decoder the multiplexer selects the respective write-ready signal for input to the pop control terminal, and a top word is popped from the FIFO.