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US 7,743,084 B2Granted
Processing unit having multioperand decimal addition
AssigneeWisconsin Alumni Research Foundation
InventorsMichael J. Schulte, Robert D. Kenney
Life of this patent
Estimating the term…
Abstract
A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.
Claims33
A method comprising:
- receiving, in parallel, at least three decimal operands wit a decimal multioperand adder circuit of a processing circuit;
- performing binary carry-save addition with the decimal multioperand adder circuit to produce a set of sum bits and a set of carry bits by:
- performing a binary carry-save addition with at least two of the decimal operands,
- correcting one of the other decimal operands to produce a corrected version of the other one of the operands in parallel to performing the binary carry-save addition of the at least two operands, and
- selectively adding a result of the binary carry-save addition for the at least two operands with either the other one of the decimal operands or the corrected version of the other one of the operands based on a most significant bit of the carry bits to produce the set of sum bits and the set of carry bits;
- and
- outputting a decimal result based on the set of sum bits and the set of carry bits,
4 more elements
A processing circuit comprising a multi-operand decimal adder circuit that:
- receives, in parallel, at least three decimal operands;
- and
- performs binary carry-save addition on the operands producing a decimal result by:
- performing a binary carry-save addition with at least two of the decimal operands,
- correcting one of the other decimal operands producing a corrected version of the other one of the operands in parallel to performing the binary carry-save addition of the at least two operands, and
- selectively adding a result of the binary carry-save addition for the at least two operations with either the other one of the decimal operands or the corrected version of the other one of the operands based on a most significant bit of the carry bits to produce the set of sum bits and the set of carry bits.
3 more elements
A method comprising:
- (a) receiving at least three decimal operands with a decimal multioperand adder circuit of a processing circuit;
- (b) adding a digit of a first one of the operands with a digit of a second one of the operands with a first binary carry-save adder circuit to produce an intermediate sum and an intermediate carry;
- (c) adding a digit of a third one of the operands with a correction value in parallel with the execution of step (b) to produce a corrected version of the third one of the operands;
- and
- (d) selectively adding either the third one of the operands or the corrected version to the intermediate sum of step (b) with a second binary carry-save adder circuit based on the most significant bit of the intermediate carry from step (b).
2 more elements
A multi-operand decimal adder circuit comprising:
- a plurality of input circuits receiving a plurality of decimal operands;
- a first binary carry-save adder circuit that adds a digit of a first one of the operands with
- a digit of a second one of the operands to produce a first intermediate sum and a first intermediate carry;
- a correction circuit executing in parallel to the first binary carry-save adder circuit producing a corrected version of a third operand;
- a multiplexer circuit selectively outputting either the third one of the operands or the corrected version of the third operand based on the most significant bit of the first intermediate carry;
- and
- a second binary carry-save adder circuit to add the first intermediate sum and the first intermediate carry with the output of the multiplexer circuit.
4 more elements
A method comprising:
- (a) receiving at least four decimal operands with a decimal adder circuit of a processing circuit;
- (b) adding a digit of a first one of the operands with a digit of a second one of the operands with a first binary carry-save adder circuit to produce an intermediate sum S1 and an intermediate carry C1;
- (c) adding the intermediate sum S1 and the intermediate carry C1 with a digit of a third one of the operands with a second binary carry-save adder circuit to produce an intermediate sum S2 and an intermediate carry C2;
- (d) adding a digit of a fourth one of the operands with a correction value in parallel with performance of steps (b) and (c) to produce a corrected version of the fourth one of the operands;
- and
- (e) selectively adding either the fourth one of the operands or the corrected version to the intermediate sum S2 and the intermediate carry C2 with a third binary carry-save adder circuit based on the most significant bit of the intermediate carry C1.
3 more elements
A multi-operand decimal adder circuit comprising:
- a plurality of input circuits to receive a plurality of decimal operands;
- a first binary carry-save adder circuit that adds a digit of a first one of the operands with a digit of a second one of the operands to produce a first intermediate sum S1 and a first intermediate carry C1;
- a second binary carry-save adder circuit that adds the intermediate sum S 1 and the first intermediate carry C 1 with a digit of a third one of the operands to produce a second intermediate sum $2 and a second intermediate carry C2;
- a correction circuit in parallel the first binary carry-save adder circuit and the second binary carry-save adder circuit that outputs a corrected version of a fourth operand;
- a multiplexer circuit selectively outputting either the fourth one of the operands or the corrected version of the fourth operand based on the second intermediate carry C2;
- and
- a third binary carry-save adder circuit adding the output from the multiplexer with the second intermediate sum $2 and the second intermediate carry C2 based on a logical value of the most significant bit of the first intermediate carry C1.
4 more elements
A method comprising:
- (a) receiving a plurality of decimal operands with a decimal adder circuit of a processing circuit;
- (b) adding a first subset of the operands with a first decimal speculative adder circuit to produce an intermediate sum S0 and an intermediate carry C0;
- (c) adding a second subset of the operands with a second decimal speculative adder circuit in parallel with step (b) to produce an intermediate sum S1 and an intermediate carry C1,
- wherein the first and second speculative adder circuits each performs binary carry-save addition by:
- performing a binary carry-save addition with at least two of the decimal operands,
- correcting one of the other decimal operands to produce a corrected version of the other one of the operands in parallel to performing the binary carry-save addition of the at least two operands, and
- selectively adding a result of the binary carry-save addition for the at least two operations with either the other one of the decimal operands or the corrected version of the other one of the operands based on a most significant bit of the carry bits to produce the intermediate sums S0 and S1 and intermediate carries C0 and C1, respectively;
- and
- (d) outputting a decimal result based on the intermediate sums S0 and S1 and the intermediate carries C0 and C1.
6 more elements
A multi-operand decimal adder circuit comprising:
- a plurality of input circuits receiving a plurality of decimal operands;
- a first speculative adder circuit adding a first subset of the operands to produce a first intermediate sum S1;
- a second speculative adder circuit in parallel with the first speculative adder circuit adding a second subset of the operands to produce a second inter intermediate sum S2,
- wherein the first and second speculative adder circuits each performs binary carry-save addition by:
- performing a binary carry-save addition with at least two of the decimal operands, correcting one of the other decimal operands to produce a corrected version of the other one of the operands in parallel to performing the binary carry-save addition of the at least two operands, and
- selectively adding a result of the binary carry-save addition for the at least two operations with either the other one of the decimal operands or the corrected version of the other one of the operands based on a most significant bit of the carry bits to produce the intermediate sums SO and S 1, respectively;
- and
- at least one carry propagate adder to output the decimal result as a function of the intermediate sums S 1 and S2.
5 more elements
Dependencies are inferred from the claim text.