Digital image data processing apparatus
AssigneeAten International Co., Ltd.
InventorsKai-Cheng Chan, Chun-Chieh Chen
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Abstract
The present image processing apparatus includes a pixel arrangement controller and two data unit buffers coupled with the pixel arrangement controller. This controller can rearrange the addresses of the pixels in the corresponding data unit buffer according to the size of the block. Accordingly, the pixel data of the same block can be arranged in sequential addresses of the data unit buffer. Therefore, the pixel data may be processed as a batch.
Claims20
An image processing apparatus for arranging an image with M.times.N pixels, wherein said image is divided into a plurality of (K.times.K) blocks, said apparatus comprising:
- a memory;
- and
- an arrangement controller coupled with said memory to determine addresses of said pixels in said memory, wherein pixels of the same (K.times.K) block are arranged in sequential addresses in said memory.
An image processing apparatus for arranging an image with M.times.N pixels, wherein said image is divided into a plurality of (K.times.K) blocks, said apparatus comprising:
- a first memory and a second memory;
- an arrangement controller coupled with said first memory and said second memory to determine addresses of said pixels in said first memory or said second memory, wherein said pixels are grouped by each K rows, and pixels of each group are arranged in sequential addresses in said first memory or said second memory;
- wherein said arrangement controller further comprises:
- a horizontal counter to count a horizontal number;
- a vertical counter to count a vertical number;
- a divider coupled with said horizontal counter to divide said horizontal number with K to generate a quotient and a remainder;
- a first multiplier coupled with said vertical counter to multiply said vertical number with K to generate a first result value;
- a second multiplier coupled with said divider to multiply said quotient with K.sup.2 to generate a second result value;
- and
- an adder coupled with said divider, said first multiplier and said second multiplier to add said remainder, said first result value and said second result value to generate a value of an address.
An image processing method implemented in an image processing apparatus for arranging the pixels of an image with M.times.N pixels, wherein said image is divided into a plurality of (K.times.K) blocks, said method comprising:
- (a) receiving a pixel;
- (b) determining whether or not a horizontal number of said pixel is equal to N, and performing step (c) and then step (d) when said horizontal number of said pixel is equal to N, and performing step (d) when said horizontal number of said pixel is not equal to N;
- (c) subtracting N from said horizontal number;
- (d) determining whether or not a vertical number of said pixel is equal to K, and performing step (e) and then step (f) when said vertical number of said pixel is equal to K, and performing step (f) when said vertical number of said pixel is not equal to K;
- (e) switching between a first memory and a second memory of said image processing apparatus, and setting said vertical number to zero;
- (f) calculating an address of said pixel using the following equation:
- Address=INT(horizontal number/K).times.K.times.K+(vertical number.times.K) +Mod(horizontal number, K)
- wherein the INT(horizontal number/K) means a quotient of said horizontal number divided by the K, and the Mod(horizontal number, K) means a remainder of said horizontal number divided by the K;
- and
- (g) arranging said pixel in said first memory or in said second memory based on said address.
Dependencies are inferred from the claim text.