Shrinking key generator for parallel process

A parallel processing shrinking key generator, comprising:

• a selection linear feedback shift register (LFSR) coupled to receive a clock signal for shifting a selection bit according to the clock signal;
• a source LFSR coupled to receive the clock signal for shifting a source bit according to the clock signal;
• a selection logic circuit coupled to outputs of the selection LFSR and the source LFSR for selecting, according to the selection bit outputted from the selection LFSR, one of (a) the source bit outputted from the source LFSR and (b) a predetermined input bit;
• an index counter coupled to receive the clock signal and to the output of the selection LFSR for assigning an index indicating where output bits of the selection logic circuit are to be stored to an output amount register at a next clocking of said clock signal;
• and
• the output amount register coupled to receive the clock signal and to the output of the selection logic circuit for shifting an output bit of the selection logic circuit according to the index;
• wherein the selection logic circuit includes four identical pushing logics and six identical through logics when each of the selection LFSR and the source LFSR is a 16 bit LFSR;
• wherein the selection logic circuit comprises
• a first pushing logic at a first stage,
• a second pushing logic and a first through logic at a second stage, wherein the second pushing logic and the first through logic are coupled to an output of the first pushing logic;
• a third pushing logic, a second through logic and a third through logic at a third stage, wherein
• the third pushing logic, the second through logic and the third through logic are all coupled to an output of the first through logic, and
• only the third pushing logic and the second through logic are coupled to an output of the second pushing logic;
• and
• a fourth pushing logic, a fourth through logic, a fifth through logic and a sixth through logic at a fourth stage, wherein
• the fourth pushing logic, the fourth through logic, the fifth through logic and the sixth through logic are all coupled to an output of the third through logic,
• only the fourth pushing logic, the fourth through logic, and the fifth through logic are coupled to an output of the second through logic, and
• only the fourth pushing logic and the fourth through logic are coupled to an output of the third pushing logic;
• wherein outputs of the fourth pushing logic, the fourth through logic, the fifth through logic and the sixth through logic are coupled to the output amount register;
• wherein the selection logic circuit further includes a pipeline stage register between the fourth stage and the third stage for eliminating a fan-in and fan-out problem;
• and
• wherein
• the selection LFSR outputs N bits from s[0], s[1], . . . to s[N−1], where N is great than 1;
• the source LFSR outputs N bits from a[0], a[1], . . . to a[N−1] which correspond to s[0], s[1], . . . to s[N−1], respectively;
• and
• for each bit among s[0], s[1], . . . to s[N−1] which is 1, the selection logic circuit outputs the corresponding bit among a[0], a[1], . . . to a[N−1].