US 7,742,553 B1Granted

VCO initial frequency calibration circuit and method therefore

AssigneeXilinx, Inc.

InventorsKhaldoun Bataineh, Michael Mass, Michael J. Gaboury, David E. Tetzlaff

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Abstract

A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

Claims20

Dependent claims

A transceiver for processing high data rate serial data, comprising:

clock data recovery (CDR) circuitry for receiving the high data rate serial data and recovering a clock from the high data rate serial data, the CDR circuitry further including a phase locked loop (PLL) that initially operates at an initial voltage controlled oscillator (VCO) clock frequency and subsequently operates at a frequency based upon a clock rate of the high data rate serial data;
a VCO initial frequency calibration circuit for setting the initial VCO clock frequency for the PLL of the CDR circuitry, wherein the VCO initial frequency calibration circuit sets the initial VCO clock frequency within a programmable phase locked loop lock range of the clock rate of the high data rate serial data based upon a frequency of a reference clock, and wherein the VCO initial frequency calibration circuit further comprises:
a frequency detection block for an indication of a difference between the reference clock and a divided VCO clock;
a frequency calibration block that produces a digital output signal having a magnitude based upon the indication of the difference between the reference clock and the divided VCO clock;
a digital-to-analog controller for converting the digital output signal to an n-bit VCO adjust signal, wherein the n-bit VCO adjust signal comprises an analog voltage coupled to control the initial VCO clock frequency;
and
a circuit adapted to open the PLL and close the VCO initial frequency calibration circuit to calibrate the initial VCO clock frequency, the circuit being further adapted to close the PLL and open the VCO initial frequency calibration circuit while the n-bit VCO adjust signal maintains the calibrated initial VCO clock frequency to enable the PLL to further adjust the VCO clock frequency from the calibrated initial VCO clock frequency, where the n-bit VCO adjust signal is set to an initial value which may be adjusted while calibrating the initial VCO clock frequency by the VCO initial frequency calibration circuit to enable the CDR circuitry to generate the initial VCO clock frequency within the programmable phase locked loop lock range of the clock rate of the high data rate serial data before closing the PLL and opening the VCO initial frequency calibration circuit, and wherein a phase detection module of the PLL is coupled to receive a phase of the high data rate serial data and a phase of a feedback signal, generated at an output of the PLL to enable the VCO clock frequency to correspond to the frequency of the high data rate serial data after calibrating the initial VCO clock frequency.

4 more elements

A method for processing high data rate serial data, comprising:

receiving the high data rate serial data;
setting an initial frequency of operation of a phase locked loop while the phase locked loop is opened, wherein the initial frequency is set within a programmable phase locked loop lock range of a rate of the high data rate serial data;
closing the phase locked loop;
recovering a clock from the high data rate serial data while the phase locked loop is closed;
and
wherein setting the initial frequency of operation further comprises:
setting an initial value of a signal operable to adjust a frequency of a VCO clock;
generating an indication of a difference between a reference clock and a divided VCO clock;
modifying the initial value of the signal operable to adjust the frequency of the VCO clock until the frequency of the VCO clock is within the programmable phase locked loop lock range of the rate of the high data rate serial data based upon the difference between the reference clock and the divided VCO clock;
producing a digital output signal having a magnitude based upon the indication of the difference between the reference clock and the divided VCO clock;
converting the digital output signal to an analog signal, wherein the analog signal is the signal operable to adjust the frequency of the VCO clock to the initial frequency;
maintaining the adjusted frequency of the VCO clock at the initial frequency until the phase locked loop is closed to enable the phase locked loop to further adjust the frequency of the VCO clock from the initial frequency;
comparing a phase of the high data rate serial data and a phase of a feedback signal, generated at an output of the phase locked loop;
and
enabling the frequency of the VCO clock to correspond to the frequency of the high data rate serial data based upon the comparison.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/035,773Filed 14 Jan 2005
Granted: 22 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03C 3/0991
Using a phase locked loop: including calibration means or calibration methods
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L 7/099
Details of the phase-locked loop: concerning mainly the controlled oscillator of the loop
H03L 7/113
For assuring initial synchronisation or for broadening the capture range: using frequency discriminator