Controlling timeslot delay in a digital communication system
AssigneeAgere Systems Inc.
InventorGzim Derti
Life of this patent
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Abstract
A buffer circuit for use in a digital communication system includes a memory and a controller coupled to the memory. The memory is configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system. The controller is operative to store data from the first data stream into corresponding timeslots in the memory in a first order, to individually adjust delays of the respective timeslots as a function of respective delay control parameters, and to generate a second data stream by reading the timeslots stored in the memory in a second order.
Claims20
A buffer circuit for use in a digital communication system, the buffer circuit comprising:
- a memory configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system;
- and
- a controller coupled to the memory, the controller being operative:
- (i) to store data from the first data stream into corresponding timeslots in the memory in a first order;
- (ii) to individually adjust delays of the timeslots in the memory as a function of respective delay control parameters;
- and (iii) to generate a second data stream by reading the timeslots stored in the memory in a second order;
- wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots;
- and
- wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.
An integrated circuit including at least one buffer circuit for use in a digital communication system, the at least one buffer circuit comprising:
- a memory configurable for storing a plurality of data frames of a first data stream, each of the data frames including a plurality of timeslots corresponding to respective channels in the digital communication system;
- and
- a controller coupled to the memory, the controller being operative:
- (i) to store data from the first data stream into corresponding timeslots in the memory in a first order;
- (ii) to individually adjust delays of the timeslots in the memory as a function of respective delay control parameters;
- and (iii) to generate a second data stream by reading the timeslots stored in the memory in a second order;
- wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots;
- and
- wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.
A non-transitory computer-readable storage medium for individually controlling a delay of each of a plurality of timeslots on a given link in a digital communication system, the non-transitory computer-readable storage medium containing one or more programs which when executed implement the steps of:
- storing timeslots of each of a plurality of data frames of a first data stream into corresponding timeslots in a memory in a first order;
- individually adjusting delays of the timeslots in the memory as a function of respective delay control parameters;
- and
- generating a second data stream by reading the timeslots stored in the memory in a second order;
- wherein the timeslots in the memory correspond to respective channels in the digital communication system;
- wherein at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the delay control parameters corresponding to the timeslots;
- and
- wherein the delay control parameters are functions of one or more characteristics of the respective channels in the digital communication system, such that the at least one of the first order in which data from the first data stream is stored in the memory and the second order in which the second data stream is read from the memory is a function of the one or more characteristics of the respective channels.
Dependencies are inferred from the claim text.