Internal loop-back architecture for parallel serializer/deserializer (SERDES)
AssigneeAvago Technologies Enterprise IP (Singapore) Pte. Ltd.
InventorsMichael Martin Farmer, Robert J. Martin, Peter Meier
Life of this patent
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Abstract
An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.
Claims16
An internal loop-back architecture for a parallel serializer/deserializer (SERDES), comprising:
- a transmitter macro including a plurality of transmit elements arranged in a parallel architecture;
- and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and
- wherein each of the plurality of transmit elements includes a loop-back arrangement with each of the plurality of receive elements, and
- wherein the plurality of transmit elements are individually addressable in a row and column arrangement;
- and the plurality of receive elements are individually addressable in a row and column arrangement, wherein adjoining transmit elements in a row are coupled together to access the communication channel and wherein adjoining receive elements in a row are coupled together to access the communication channel.
An internal loop-back architecture for a parallel serializer/deserializer (SERDES), comprising:
- a plurality of transmitters arranged in a parallel architecture in which adjoining transmitters can communicate with each other;
- and a plurality of receivers arranged in a parallel architecture in which adjoining receivers can communicate with each other, wherein at least a portion of the transmitters and a portion of the receivers share a communication channel and wherein any of the plurality of transmitters in a row can communicate with any of the plurality of receivers in a row, and
- wherein each of the plurality of transmitters includes a loop-back arrangement with each of the plurality of receivers, and
- wherein the plurality of transmitters are individually addressable in a row and column arrangement;
- and the plurality of receivers are individually addressable in a row and column arrangement, wherein adjoining transmitters in row are coupled together to access the communication channel and wherein adjoining receivers in a row are coupled together to access the communication channel.
A method for performing internal loop-back testing on a serializer/deserializer (SERDES), comprising:
- coupling a plurality of transmit elements arranged in a parallel architecture with a plurality of receive elements arranged in a parallel architecture such that at least a portion of the transmit elements and a portion of the receive elements share a communication channel and such that any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and
- such that each of the plurality of transmit elements includes a loop-back arrangement with each of the plurality of receive elements, and
- such that the plurality of transmit elements are individually addressable in a row and column arrangement;
- and the plurality of receive elements are individually addressable in a row and column arrangement, wherein the method comprises coupling adjoining transmit elements in a row to access the communication channel and coupling adjoining receive elements in a row to access the communication channel.
Dependencies are inferred from the claim text.