Highly-scalable hardware-based traffic management within a network processor integrated circuit

A method for managing traffic within a network processor integrated circuit (IC), the method comprising:

• within a network processor IC, establishing multiple queue groups, wherein each queue group includes multiple queues for queuing incoming traffic;
• within the network processor IC, associating a different hardware counter with each queue group, each group-specific hardware counter comprising a multi-bit register that is changed in response to a clock signal;
• within the network processor IC, establishing an initial value for each group-specific hardware counter, wherein the initial value establishes a group-specific time interval for each queue group and wherein the length of a group-specific time interval is a function of the initial value and a clock period of a clock signal;
• within the network processor IC, rate shaping traffic within the queues of the queue groups in response to the group-specific hardware counters associated with the queue groups, wherein the rate shaping comprises establishing an initial credit value for each queue and tracking a current credit value for each queue, wherein the initial credit value indicates available credit per group-specific time interval and the current credit value represents available credit at a particular point within the group-specific time interval;
• and
• within the network processor IC, scheduling traffic within queues of the queue groups in response to the group-specific hardware counters associated with the queue groups.