Calibration circuit of a semiconductor memory device and method of operating the same

Abstract

A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated circuit without receiving data from the outside, a PRBS tester that compares output signals of a data latch that strobes and latches an output signal of a data input buffer to determine whether the interlock operation of data and strobe is pass or fail, and a calibration unit that calibrates a delay time using the output signal of the PRBS tester as much as a predetermined unit. Thus, variation in process, voltage, temperature, etc. can be freely calibrated even after package assembly. Accordingly, it is possible to guarantee a set-up/hold value that is necessary for high frequency operation of a system, and to reduce the time and resources necessary for product manufacture and for calibrating these values.

Dependencies are inferred from the claim text.