# US 7,742,357 B2 · Securing an integrated circuit

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- Number: US 7,742,357 B2
- Document ID: US7742357B2
- Status: Granted
- Kind: B2
- Application number: 11/381,824
- Filed: 2006-05-05
- Published: 2007-11-08
- Granted: 2010-06-22
- Earliest claimed: 2006-05-05
- Assignees: International Business Machines Corporation
- Inventors: Robert C. Dixon; Kirk E. Morrow; Phil C. F. Paone
- Web page: https://patentgrep.com/patent/US7742357B2

## CPC

- G11C 29/46: Test trigger logic
- G11C 29/1201: {comprising I/O circuitry}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Securing an integrated circuit, including fabricating the integrated circuit to include a multiplicity of unblown efuses, at least one surrogate efuse that emulates a blown efuse, non-volatile data representing the blown state of the surrogate efuse, and security circuitry; and setting, by the security circuitry when power is first applied to the integrated circuit, a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

## Claims

### Claim 1

A method for securing an integrated circuit, the method comprising:
fabricating the integrated circuit to include a multiplicity of unblown efuses, at least one surrogate efuse that emulates a blown efuse, non-volatile data representing the blown state of the surrogate efuse, and security circuitry; and
setting, by the security circuitry when power is first applied to the integrated circuit, a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

### Claim 2 (depends on 1)

The method of claim 1 wherein setting a security state of the integrated circuit is carried out by a state machine of the security circuitry.

### Claim 3 (depends on 1)

The method of claim 1 further comprising carrying out the following steps when power is first applied to the integrated circuit:
reading by the security circuitry the sensed state of the surrogate efuse from a sensing circuit;
reading by the security circuitry the non-volatile data representing the blown state of the surrogate efuse; and
determining by the security circuitry whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

### Claim 4 (depends on 1)

The method of claim 1 wherein setting a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse further comprises:
setting the security state to a fabrication test security state if the sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse; and
setting the security state to a blocked security state if the sensed state of the surrogate efuse is not equal to the blown state of the surrogate efuse.

### Claim 5 (depends on 1)

The method of claim 1 wherein the integrated circuit is characterized by a multiplicity of security states, including a fabrication test security state, an original equipment manufacturer (‘OEM’) security state, a normal operations security state, a maintenance test security state, and a blocked security state.

### Claim 6 (depends on 1)

The method of claim 1 wherein fabricating the integrated circuit further comprises fabricating the integrated circuit with no wafer-only pin (‘WOP’) to enable blowing efuses after fabrication of the integrated circuit.

### Claim 7 (depends on 1)

The method of claim 1 wherein the surrogate efuse comprises a resistor of the integrated circuit having a resistance that emulates a blown efuse.

### Claim 8

Apparatus for securing an integrated circuit, the apparatus comprising:
an integrated circuit fabricated to include a multiplicity of unblown efuses, at least one surrogate efuse that emulates a blown efuse, non-volatile data representing the blown state of the surrogate efuse, and security circuitry; and
security circuitry capable of setting, when power is first applied to the integrated circuit, a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

### Claim 9 (depends on 8)

The apparatus of claim 8 security circuitry capable of setting a security state of the integrated circuit implements a state machine for:
reading the sensed state of the surrogate efuse from a sensing circuit;
reading the non-volatile data representing the blown state of the surrogate efuse;
determining whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse; and
setting a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

### Claim 10 (depends on 8)

The apparatus of claim 8 further comprising security circuitry capable of carrying out the following steps when power is first applied to the integrated circuit:
reading the sensed state of the surrogate efuse from a sensing circuit;
reading the non-volatile data representing the blown state of the surrogate efuse; and
determining whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

### Claim 11 (depends on 8)

The apparatus of claim 8 wherein setting a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse further comprises:
setting the security state to a fabrication test security state if the sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse; and
setting the security state to a blocked security state if the sensed state of the surrogate efuse is not equal to the blown state of the surrogate efuse.

### Claim 12 (depends on 8)

The apparatus of claim 8 wherein the integrated circuit is characterized by a multiplicity of security states, including a fabrication test security state, an original equipment manufacturer (‘OEM’) security state, a normal operations security state, a maintenance test security state, and a blocked security state.

### Claim 13 (depends on 8)

The apparatus of claim 8 wherein the integrated circuit is further fabricated with no wafer-only pin (‘WOP’) to enable blowing efuses after fabrication of the integrated circuit.

### Claim 14 (depends on 8)

The apparatus of claim 8 wherein the surrogate efuse comprises a resistor of the integrated circuit having a resistance that emulates a blown efuse.