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US 7,742,356 B2Granted
Semiconductor memory device having a refresh cycle changing circuit
AssigneeElpida Memory, Inc.
InventorsChiaki Dono, Yasuji Koshikawa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.
Claims8
A semiconductor memory device, comprising:
- a plurality of memory cells requiring a refresh operation so as to hold stored information;
- and
- a refresh circuit performing the refresh operation to memory cells connected to a predetermined number of word lines in a first refresh mode and performing the refresh operation to memory cells connected to less than the predetermined number of word lines in a second fresh mode,
- wherein the refresh operation in the first refresh mode is performed in response to an external refresh command supplied from outside the semiconductor memory device and the refresh operation in the second refresh mode is performed in response to an internal refresh command generated automatically in the semiconductor memory device,
- wherein the refresh circuit includes a first refresh cycle changing circuit and a second refresh cycle changing circuit,
- wherein the first refresh cycle changing circuit performs the refresh operation to the memory cells connected to the predetermined number of word lines in the first refresh mode, and
- wherein the second refresh cycle changing circuit performs the refresh operation to the memory cells connected to less than the predetermined number of word lines in the second refresh mode.
4 more elements
A semiconductor memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells each disposed at an associated intersection of the word lines and the bit lines;
- a refresh circuit performing a refresh operation to refresh memory cells selected from said plurality of memory cells when a refresh request signal is activated;
- a program circuit controlling the refresh circuit so as to perform the refresh operation to selected memory cells connected to a first number of word lines in a first mode every time the refresh request signal is activated and controlling the refresh circuit so as to perform the refresh operation to selected memory cells connected to a second number different from the first number of word lines in a second mode when the refresh request signal is activated;
- a refresh request signal generator generating a second refresh request signal;
- and
- a second program circuit controlling the refresh circuit so as to perform the refresh operation to selected memory cells connected to a third number of word lines in a third mode when the second refresh request signal is activated, and controlling the refresh circuit to perform the refresh operation to selected memory cells connected to a fourth number of word lines different from the third number of word lines in a fourth mode when the second refresh request signal is activated,
- wherein the program circuit includes a first nonvolatile memory element,
- wherein the first mode is selected when the first nonvolatile memory element is in a first state,
- wherein the second mode is selected when the first nonvolatile memory element is in a second state, and
- wherein the refresh request signal is activated, every time an external command is issued from outside the semiconductor memory device.
9 more elements
A semiconductor memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells each disposed at an associated intersection of the word liens and the bit lines;
- a refresh circuit performing a refresh operation to refresh memory cells selected from said plurality of memory cells when a refresh request signal is activated;
- and
- a program circuit controlling the refresh circuit so as to perform the refresh operation to selected memory cells connected to a first number of word lines in a first mode every time the refresh request signal is activated and controlling the refresh circuit so as to perform the refresh operation to selected memory cells connected to a second number different from the first number of word lines in a second mode when the refresh request signal is activated. wherein a refresh cycle in the first mode is longer than a refresh cycle in the second mode.
3 more elements
Dependencies are inferred from the claim text.