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US 7,742,345 B2Granted
Data input circuit of semiconductor memory apparatus and method of inputting the data
AssigneeHynix Semiconductor Inc.
InventorKi-Chang Kwean
Life of this patent
Estimating the term…
Abstract
A data input circuit for a semiconductor memory apparatus includes a write latency control unit configured to generate a buffer enable signal based on a low frequency operation mode signal, and a data input buffer configured to buffer input data in response to the buffer enable signal.
Claims23
A data input circuit for a semiconductor memory apparatus, comprising:
- a write latency control unit configured to generate a buffer enable signal, and to vary an enable period of the buffer enable signal based on a low frequency operation mode signal when a length of a write latency is shorter than a predetermined length;
- and
- a data input buffer configured to buffer input data in response to the buffer enable signal.
A data input circuit for a semiconductor memory apparatus comprising:
- a write latency control unit configured to generate a buffer enable signal in accordance with a write latency in a high frequency operation mode, and to generate the buffer enable signal regardless of the write latency in a low frequency operation mode;
- and
- a data input buffer configured to buffer input data in response to the buffer enable signals wherein the write latency control unit is configured to generate a write enable signal from a write command and a burst end signal, and output the write enable signal as the buffer enable signal regardless of a length of the write latency in the low frequency mode and is configured to further generate a row enable signal from a row active command and a row precharge command, output the row enable signal as the buffer enable signal if the length of the write latency is shorter than a predetermined length in the high frequency operation mode, and output the write enable signal as the buffer enable signal if the length of the write latency is longer than the predetermined length in the high frequency operation mode.
A data input method of a semiconductor memory apparatus comprising:
- generating a row enable signal from a row active command and a row precharge command and a write enable signal from a write command and a burst end signal;
- passing the row enable signal and the write enable signal in a high frequency operation mode, and passing only the write enable signal in a low frequency operation mode;
- outputting the passed row enable signal or the passed write enable signal as a buffer enable signal when a write latency is shorter than a predetermined length, and outputting the passed write enable signal as the buffer enable signal when the write latency is longer than the predetermined length;
- and
- buffering input data using the buffer enable signal.
2 more elements
Dependencies are inferred from the claim text.