Biasing circuit for EEPROM memories with shared latches

An EEPROM memory comprising a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines, wherein each biasing element comprises a first switch for providing the biasing signal at a programming voltage, a memory element for providing a programming enabling signal that controls the first switch, and a plurality of second switches each for coupling the first switch with a corresponding one of the associated data lines, the second switches being controlled by corresponding selection signals of the associated packets.

An EEPROM memory comprising a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines, wherein the matrix has a plurality of rows, the memory cells of each row associated with one packet defining a word, and wherein the EEPROM memory further comprises a plurality of selection lines each coupled with the words of a corresponding packet, a plurality of further biasing elements for providing a further biasing signal to the selection lines, and means for selecting the further biasing element for the selected packet, each further biasing element being associated with the selection lines corresponding to a plurality of packets and comprising further switching means for selectively providing the further biasing signal to a selected one of the associated selection lines.

An operating method of an EEPROM memory comprising a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, and a plurality of biasing elements for providing a biasing signal to the data lines, each biasing element being associated with corresponding data lines of a plurality of packets, the method comprising:

• selecting the biasing elements for a selected one of the packets,
• selectively applying the biasing signal to a selected one of the data lines associated with each selected biasing element, and selectively applying a clamped signal to each non-selected one of the associated data lines.