Local self-boost inhibit scheme with shielded word line

A method of drain-side self boost programming in a NAND architecture memory device, comprising:

• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming;
• applying a cutoff voltage to a first set of two or more unselected word lines, wherein the first set of two or more unselected word lines are directly adjacent to each other and where the first set of two or more unselected word lines are between the selected word line and a source line;
• applying a first pass voltage to a second set of one or more unselected word lines, wherein the second set of one or more unselected word lines are between the first set of two or more unselected word lines and the source line;
• and
• applying a second pass voltage to one or more remaining word lines of the memory string;
• wherein the first pass voltage is between the second pass voltage and a ground potential.

A non-volatile NAND architecture memory device comprising:

• a NAND architecture non-volatile memory array having a plurality of memory blocks;
• and
• a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by,
• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string of the array that is selected for programming;
• applying a cutoff voltage to a first set of two or more word lines located between the selected word line and a source line coupled to the memory string, wherein the first set of two or more word lines are directly adjacent to each other;
• applying a first pass voltage to remaining word lines between the first set of two or more word lines and the source line;
• and
• applying a second pass voltage to a second set of one or more word lines of the memory string located between the selected word line and a bit line coupled to the memory string;
• wherein the first pass voltage is between the second pass voltage and a ground potential.

A system comprising:

• a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,
• a NAND architecture non-volatile memory array having a plurality of blocks;
• wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by,
• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string of the array that is selected for programming;
• applying a cutoff voltage to a first set of two or more word lines located between the selected word line and a source line coupled to the memory string, wherein the first set of two or more word lines are directly adjacent to each other;
• applying a first pass voltage to remaining word lines between the first set of two or more word lines and the source line;
• and
• applying a second pass voltage to a second set of one or more word lines located between the selected word line and a bit line coupled to the memory string;
• wherein the first pass voltage is between the second pass voltage and a ground potential.

A method of drain-side self boost programming in a NAND architecture memory device, comprising:

• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming;
• applying a cutoff voltage to a first set of two or more unselected word lines, wherein the first set of two or more unselected word lines are directly adjacent to each other and where the first set of two or more unselected word lines are between the selected word line and a source line;
• applying a pass voltage to one or more remaining word lines of the memory string;
• and
• applying a second pass voltage to a second set of one or more unselected word lines, wherein the second set of one or more unselected word lines are between the first set of two or more unselected word lines and the selected word line, and where the second pass voltage is between the pass voltage and a ground potential.

A method of drain-side self boost programming in a NAND architecture memory device, wherein the drain-side self boost is a local self boost, the method comprising:

• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming;
• applying a cutoff voltage to a first set of two or more unselected word lines, wherein the first set of two or more unselected word lines are directly adjacent to each other and where the first set of two or more unselected word lines are between the selected word line and a source line;
• applying a pass voltage to one or more remaining word lines of the memory string;
• and
• applying the cutoff voltage to a second set of two or more unselected word lines, wherein the second set of two or more word lines are directly adjacent to each other and where the second set of two or more unselected word lines are between the selected word line and a bit line.

A non-volatile NAND architecture memory device comprising:

• a NAND architecture non-volatile memory array having a plurality of memory blocks;
• and
• a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by,
• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string of the array that is selected for programming;
• applying a cutoff voltage to a first set of two or more word lines, wherein the first set of two or more word lines are directly adjacent to each other;
• applying a first pass voltage to one or more remaining word lines between the first set of two or more source-side adjacent word lines and the source line;
• and
• applying a second pass voltage to a second set of one or more unselected word lines,
• wherein the second set of one or more unselected word lines are between the first set of two or more unselected word lines and the selected word line and where the second pass voltage is between the first pass voltage and a ground potential.

A system comprising:

• a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,
• a NAND architecture non-volatile memory array having a plurality of blocks;
• wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by,
• applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string of the array that is selected for programming;
• applying a cutoff voltage to a first set of two or more unselected word lines, wherein the first set of two or more unselected word lines are directly adjacent to each other and between the selected word line and a source line;
• applying a first pass voltage to one or more remaining word lines between the first set of two or more unselected word lines and the source line;
• and
• applying a second pass voltage to a second set of one or more unselected word lines, wherein the second set of one or more unselected word lines are between the at least one first set of one or more unselected word lines and the selected word line, and where the second pass voltage is between the first pass voltage and a ground potential.