Phase-change random access memory device and semiconductor memory device

A phase-change random access memory device comprising:

• a plurality of word lines arranged in parallel with each other;
• a plurality of local bit lines arranged in parallel with each other above the word lines and orthogonal to the word lines;
• a plurality of memory cells arranged parallel to the word lines and parallel to the local bit lines, each of the memory cells including a phase-change element and a diode connected in series with the local bit line;
• a plurality of first and second common drain lines arranged below the plurality of memory cells in parallel with the word lines, and commonly connecting a predetermined number of the memory cells that are orthogonal to the local bit lines;
• a plurality of global bit lines arranged below the first and second common drain lines and in parallel with the local bit lines;
• a plurality of first switching transistors each having a gate connected to associated one of the word lines, a drain connected to one of the global bit lines, and a source connected to associated one of the first common drain lines;
• and
• a plurality of second switching transistors each having a gate connected to associated one of the word lines, a drain connected to one of the global bit lines, and a source connected to associated one of the second common drain lines, the first switching transistors and the second switching transistors being arranged in alternation with each other, and connected to different global bit lines.

A semiconductor memory device comprising:

• first and second wiring layers extending substantially parallel to each other in a first direction;
• a first semiconductor region formed in a part of a portion that is between the first and second wiring layers;
• a second semiconductor region formed on an opposite side to the first semiconductor region with respect to the second wiring layer and making a pair with the first semiconductor region;
• a third semiconductor region formed in another part of the portion that is between the first and second wiring layers;
• a fourth semiconductor region formed on an opposite side to the third semiconductor region with respect to the first wiring layer and making a pair with the third semiconductor region;
• a third wiring layer extending in a second direction that crosses the first direction and having an electrical contact with the first semiconductor region;
• a fourth wiring layer extending in the second direction and having an electrical contact with the fourth semiconductor region;
• a fifth wiring layer extending in the first direction to cross over the first and third semiconductor regions and having an electrical contact with the third semiconductor region;
• a sixth wiring layer extending in the first direction in substantially parallel to the fifth wiring layer to cross over the second semiconductor region and having an electrical contact with the second semiconductor region;
• a plurality of seventh wiring layers extending in the second direction in substantially parallel to one another, each of the seventh wiring layers intersecting each of the fifth and sixth wiring layers;
• a plurality of first memory elements each disposed at an intersection of an associated one of the seventh wiring layers and the fifth wiring layer;
• and
• a plurality of second memory elements each disposed at an intersection of an associated one of the seventh wiring layers and the sixth wiring layer.

A semiconductor memory device comprising:

• a plurality of memory cell array areas arranged in a plurality of rows and columns;
• plural sets of bit lines, each of the sets of the bit lines being provided correspondingly to each of the rows of the memory cell array areas and extending in a first direction substantially parallel to one another to cross a corresponding one of the rows of the memory cell array areas;
• and
• plural pairs of word lines, each of the pairs of the word lines being provided correspondingly to each of the columns of the memory cell areas and extending in a second direction substantially parallel to each other to cross a corresponding one of the columns of the memory cell array areas, the second direction crossing the first direction, each of the memory cell array areas including:
• a pair of first lines extending in the second direction substantially parallel to each other to intersect each of the bit lines that crosses a corresponding one of the memory cell array areas;
• a plurality of memory elements each disposed at an associated one of the intersections of the first lines and the bit lines that cross a corresponding one of the memory cell array areas;
• a pair of second lines extending in the first direction in substantially parallel to each other;
• a first transistor connected between one of the first lines and one of the second lines and having a gate connected to one of a corresponding pair of the word lines that cross a corresponding one of the memory cell array areas;
• and
• a second transistor connected between the other of the first lines and the other of the second lines and having a gate connected to the other of the corresponding pair of the word lines that cross a corresponding one of the memory cell array areas.