Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell

A computer-readable medium encoding an apparatus, the encoded apparatus comprising:

• a plurality of bit line structures;
• a plurality of word lines structures intersecting said plurality of bit line structures to form a plurality of cell locations;
• a plurality of cells located at said plurality of cell locations, each of said cells in turn comprising:
• a first field effect transistor (FET) of a first type, said first FET having a first drain-source terminal, a second drain-source terminal, and a gate;
• a second FET of said first type, said second FET having a first drain-source terminal, a second drain-source terminal, and a gate;
• a third FET of a second type, said third FET having a first drain-source terminal coupled to said second drain-source terminal of said second FET and said gate of said first FET to form a node Q, a second drain-source terminal, and a gate coupled to said gate of said second FET and said second drain-source terminal of said first FET to form a node Qb;
• a fourth FET having a first drain-source terminal connected to said node Q, a second drain-source terminal, and a gate;
• and
• a fifth FET having a first drain-source terminal connected to said node Qb, a second drain-source terminal, a front gate, and a back gate, independent of said front gate, and connected to said node Q;
• wherein each of said cells is selectively coupled to a corresponding one of said bit line structures via said fourth and fifth FETS, under control of a corresponding one of said word line structures acting on at least one of said front gate of said fifth FET and said gate of said fourth FET, and wherein said gate of said first FET is a front gate, said first FET also having a back gate independent of said front gate, said back gate of said first FET being interconnected with said first drain-source terminal of said first FET.

A computer-readable medium encoding an apparatus, the encoded apparatus comprising a memory cell for interconnection with a bit line structure and a word line structure, said cell in turn comprising:

• a first inverter having first and second field effect transistors (FETS);
• and
• a second inverter having third and fourth FETS, said second inverter being cross-coupled to said first inverter to form a storage flip-flop;
• wherein said second FET is configured with independent front and back gates, one of said front gate and said back gate of said second FET being configured to aid selective coupling of said cell to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, another of said front gate and said back gate of said second FET being configured for said cross-coupling with said second inverter.