Wiring structure of laminated capacitors
AssigneeIndustrial Technology Research Institute
InventorsChien-Min Hsu, Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lai
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AssigneeIndustrial Technology Research Institute
InventorsChien-Min Hsu, Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lai
Estimating the term…
The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.
A laminated capacitor, comprising:
A laminated capacitor embedded in a circuit board, comprising:
An integrated circuit substrate to which an integrated circuit chip is electrically coupled, comprising:
Dependencies are inferred from the claim text.