ESD/EOS protection circuit and related integrated circuit
AssigneeALi Corporation
InventorsYu-Chen Chen, Jen-Hao Pan, Chih-Kuo Sun
Life of this patent
Estimating the term…
Abstract
An ESD/EOS protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit is coupled between an I/O pad and a power pad and includes a first P-type transistor. The P-type transistor includes a control node, a floating gate, a first connection node, and a second connection node, wherein the first connection node of the first P-type transistor is coupled to the power pad and the second connection node of the first P-type transistor is coupled to the I/O pad. The second protection circuit is coupled between the I/O pad and a ground pad.
Claims11
An ESD/EOS protection circuit, comprising:
- a first protection circuit, coupled between an I/O pad and a power pad, the first protection circuit comprising:
- a first P-type transistor having a control node, a first connection node, and a second connection node, wherein the control node of the first P-type transistor is coupled to a bias voltage, the first connection node of the first P-type transistor is coupled to the power pad, and the second connection node of the first P-type transistor is coupled to the I/O pad;
- and
- a third P-type transistor, having a control node, a first connection node and a second connection node, where the control node of the third P-type transistor is coupled to the ground pad, the second connection node of the third P-type transistor is coupled to the control node of the first P-type transistor, and the first connection node of the third P-type transistor is floating, the third P-type transistor is used for providing the bias voltage to the first P-type transistor;
- and
- a second protection circuit, coupled between the I/O pad and a ground pad.
An integrated circuit with ESD/EOS protection, comprising:
- an internal circuit, coupled to an I/O pad, a power pad, and a ground pad of the integrated circuit;
- a first protection circuit, coupled between the I/O pad and the power pad, the first protection circuit comprising:
- a first P-type transistor having a control node, a first connection node, and a second connection node, wherein the control node of the first P-type transistor is coupled to a bias voltage, the first connection node of the first P-type transistor is coupled to the power pad, and the second connection node of the first P-type transistor is coupled to the I/O pad;
- and
- a third P-type transistor, having a control node, a first connection node and a second connection node, where the control node of the third P-type transistor is coupled to the ground pad, the second connection node of the third P-type transistor is coupled to the control node of the first P-type transistor, and the first connection node of the third P-type transistor is floating, the third P-type transistor is used for providing the bias voltage to the first P-type transistor;
- and
- a second protection circuit, coupled between the I/O pad and the ground pad.
Dependencies are inferred from the claim text.