US 7,742,024 B2Granted

Element substrate and light emitting device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsRyota Fukumoto, Aya Anzai, Yu Yamazaki, Mitsuaki Osame

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Abstract

No need of lowering off-current of a switching transistor, fewer luminance variations of a light emitting element between pixels due to characteristic variations of a driving transistor, and less risk of steps due to increase in the number of wirings. A video signal for light emission or non-emission of a pixel is input to a gate of a current controlling transistor operated in a linear region, which is connected in series with the driving transistor, through a switching transistor. Since a voltage Vds between a source and a drain of the current controlling transistor is small, small changes in a voltage Vgs between a gate and a source thereof do not affect a current flowing in a load. The current flowing in the light emitting element is determined by the driving transistor operated in a saturation region, and a fixed potential is input to the gate thereof during light emission.

Claims18

Dependent claims

A display device comprising:

a signal line;
a power source;
a power supply line;
a first wiring;
a second wiring;
a third wiring;
a first pixel comprising a first transistor, a second transistor, and a first light emitting element;
and
a second pixel comprising a third transistor, a fourth transistor, and a second light emitting element,
wherein a first region of a gate of the first transistor is electrically connected to the power source through the first wiring,
wherein a second region of the gate of the first transistor is electrically connected to a first region of a gate electrode of the third transistor through the second wiring,
wherein a second region of the gate of the third transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first light emitting element and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the second light emitting element and the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the power supply line and a gate of the second transistor is electrically connectable to the signal line, and
wherein the other of the source and the drain of the fourth transistor is electrically connected to the power supply line and a gate of the fourth transistor is electrically connectable to the signal line.

13 more elements

A display device comprising:

a signal line;
a power source;
a power supply line;
a first wiring;
a second wiring;
a third wiring;
a first pixel comprising a first transistor, a second transistor, a third transistor and a first light emitting element;
and
a second pixel comprising a fourth transistor, a fifth transistor, a sixth transistor, and a second light emitting element,
wherein a first region of a gate of the first transistor is electrically connected to the power source through the first wiring,
wherein a second region of the gate of the first transistor is electrically connected to a first region of a gate electrode of the fourth transistor through the second wiring,
wherein a second region of the gate of the fourth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first light emitting element and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second light emitting element and the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the power supply line and a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the power supply line and a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the signal line, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the signal line.

15 more elements

A display device comprising:

a signal line;
a first scan line;
a second scan line;
a power source;
a power supply line;
a first wiring;
a second wiring;
a third wiring;
a first pixel comprising a first transistor, a second transistor, a third transistor and a first light emitting element;
and
a second pixel comprising a fourth transistor, a fifth transistor, a sixth transistor, and a second light emitting element,
wherein a first region of a gate of the first transistor is electrically connected to the power source through the first wiring,
wherein a second region of the gate of the first transistor is electrically connected to a first region of a gate electrode of the fourth transistor through the second wiring,
wherein a second region of the gate of the fourth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first light emitting element and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second light emitting element and the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the power supply line and a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the power supply line and a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the signal line and a gate of the third transistor is electrically connected to the first scan line, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the signal line and a gate of the sixth transistor is electrically connected to the second scan line.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/549,946Filed 16 Oct 2006 · continuation
Priority: JP 2003-17414118 Jun 2003
Published: US 2007/0241992 A118 Oct 2007
Granted: 22 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G09G 5/006
Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto: details of…
G09G 3/3233
Using an active matrix: with pixel circuitry controlling the current through the light-emitting element
G09G 3/3275
Organic, e.g. using organic light-emitting diodes [OLED]: details of drivers for data electrodes
G09G 3/2022
By time modulation using two or more time intervals: using sub-frames

Family

Application10/866,081Parent of this continuation · filed 14 Jun 2004
US 2007/0241992 A1Pre-grant publication · published 18 Oct 2007
US 7,122,969 B2Parent of this continuation
US 2004/0256997 A1Published application
US 7,742,024 B2This patent

From the US filing history. Foreign family members aren’t listed.