Method for controlling delay time of pulse delay circuit and pulse delay circuit thereof
AssigneeDenso Corporation
InventorsTakamoto Watanabe, Shigenori Yamauchi
Life of this patent
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Abstract
An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.
Claims12
A method for driving a pulse delay circuit that generates propagation delay for a pulse signal to be transmitted through the pulse delay circuit, comprising steps of:
- preparing a plurality of delay units connected to each other to be configured as the pulse delay circuit for giving the propagation delay to the pulse signal that is successively delayed by each of the delay units, each delay unit comprising plurality of transistors that include a specific transistor having first and second terminals;
- and
- driving the first and second terminals of the specific transistor with a first and second signals respectively in order to change a delay time of the each delay unit, wherein the voltages of the first and second signals are controlled separately in order to produce a change in on-resistance of the specific transistor that causes a change in the delay time of each delay unit such that the change in the on-resistance of the specific transistor is greater than that when the first and second terminal of the specific transistor are electrically tied together.
A pulse delay circuit configured by delay units serially connected in a plurality of stages or connected to form a ring circuit, a delay unit delaying a pulse signal by a delay time based on a voltage level of a drive signal, and transmits the pulse signal while successively delaying the pulse signal by the delay time of the delay unit, comprising:
- a gate circuit that has at least one gate circuit arranged in the delay unit, the gate circuits are serially connected in a plurality of stages, the gate circuit including at least one specific transistor configured by a metal-oxide semiconductor of which the gate is driven by the pulse signal and of which the source is driven by the drive signal;
- and
- a control terminal for applying a control signal to a back gate of the specific transistor, the control terminal being arranged in the pulse delay circuit, the control signal used to control a back gate voltage to produce a change in on-resistance of the specific transistor in relation to a voltage level of the drive signal greater than that when the back gate voltage and a source voltage of the specific transistor are electrically tied together.
Dependencies are inferred from the claim text.