# US 7,741,923 B2 · Transistor voltage-controlled oscillator and frequency synthesizer having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,741,923 B2 - Document ID: US7741923B2 - Status: Granted - Kind: B2 - Application number: 12/048,574 - Filed: 2008-03-14 - Published: 2009-06-04 - Granted: 2010-06-22 - Earliest claimed: 2007-11-30 - Assignees: National Taiwan University - Inventors: Ping-Yuan Deng; Jean-Fu Kiang - Web page: https://patentgrep.com/patent/US7741923B2 ## CPC - H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider} - H03B 5/1212: {the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair} - H03B 5/1228: {the amplifier comprising one or more field effect transistors} - H03B 5/1265: {switched capacitors} - H03L 7/099: concerning mainly the controlled oscillator of the loop - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03L 7/107: using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth - H03L 7/193: the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider - H03L 7/24: using a reference signal directly applied to the generator - H03B 2200/0038: including a current mirror - H03B 2200/0074: Locking of an oscillator by injecting an input signal directly into the oscillator - H03B 2201/0266: the means comprising a transistor - H03J 2200/10: Tuning of a resonator by means of digitally controlled capacitor bank - H03K 3/0315: {Ring oscillators} - H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H) - H03J: TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A transistor voltage-controlled oscillator (VCO) and a frequency synthesizer having the transistor VCO are provided. The frequency synthesizer adopts a divide-by-five injection-locked frequency divider, which includes a five-stage inverter ring oscillating frequency dividing circuit for reducing the operating frequency of the oscillating signal from the VCO, thus decreasing power consumption due to counting operation of the frequency synthesizer. The transistor VCO includes three transistor switching capacitor sets connected in parallel to one another to form a parallel structure. The gates of the transistor switching capacitor sets are connected to respective operating voltage sources, so as to switch the status of the corresponding transistor switching capacitor set, which in turn adjusts the harmonic frequency generated by the VCO, thereby allowing the VCO to generate a corresponding operating frequency with enough bandwidth. ## Claims ### Claim 1 A frequency synthesizer, comprising: a reference signal source for providing a reference signal; a voltage-controller oscillator (VCO) for generating an oscillating signal and a first analog signal identical to the oscillating signal; an injection-locked frequency divider including a five-stage inverter ring oscillating frequency dividing circuit, the five-stage inverter ring oscillating frequency dividing circuit receives the first analog signal from the VCO and divides the frequency of the first analog signal by five, to generate a first frequency-divided signal; a pulse-swallow frequency divider for receiving the first frequency-divided signal and generating a second frequency-divided signal; a phase frequency detector (PFD) for receiving the second frequency-divided signal and comparing the second frequency-divided signal with the reference signal to output two digital signals; a charge pump for receiving and comparing the two digital signals sent by the PFD to output a second analog signal; and a loop filter for receiving the second analog signal and generating a third analog signal to the VCO. ### Claim 2 (depends on 1) The frequency synthesizer of claim 1, wherein the reference signal source is a quartz oscillation module. ### Claim 3 (depends on 2) The frequency synthesizer of claim 2, wherein the reference signal output by the quartz oscillation module has a frequency equal to 4 MHz. ### Claim 4 (depends on 1) The frequency synthesizer of claim 1, further comprising at least two buffer amplifiers for amplifying the first analog signal and the first frequency-divided signal, respectively. ### Claim 5 (depends on 1) The frequency synthesizer of claim 1, wherein the injection-locked frequency divider is a divide-by-five frequency divider. ### Claim 6 (depends on 1) The frequency synthesizer of claim 1, wherein the pulse-swallow frequency divider includes an N/N+1 dual-modulus prescaler, a first variable counter and a second variable counter. ### Claim 7 (depends on 6) The frequency synthesizer of claim 6, wherein N=16, a first mode of the dual-modulus prescaler is a divide-by-16 frequency divider, while a second mode of the dual-modulus prescaler is a divide-by-17 frequency divider. ### Claim 8 (depends on 6) The frequency synthesizer of claim 6, wherein the first variable counter is a swallow counter with four bits, and the second variable counter is a program counter with five bits. ### Claim 9 (depends on 1) The frequency synthesizer of claim 1, wherein the frequency synthesizer is compatible to IEEE 802.11 protocol, and locks eight sets of oscillating signals with frequencies of 5180 MHz, 5200 MHz, 5220 MHz, 5240 MHz, 5260 MHz, 5280 MHz, 5300 MHz, and 5300 MHz, respectively. ### Claim 10 (depends on 1) The frequency synthesizer of claim 1, wherein the VCO comprises a first transistor having a first gate, a first source and a first drain; a second transistor having a second source, a second gate connected to the first drain, and a second drain connected to the first gate; a parallel capacitor switching circuit including a first transistor switching capacitor set, a second transistor switching capacitor set and a third transistor switching capacitor set connected in parallel to one another to form a parallel structure, two ends of the parallel structure forming a first switching circuit node and a second switching circuit node, respectively; a first inductive circuit having a first inductive end connected to the first switching circuit node, and a second inductive end connected to ground; and a second inductive circuit having a third inductive end connected to the second switching circuit node, and a fourth inductive end connected to ground. ### Claim 11 (depends on 10) The frequency synthesizer of claim 10, wherein the first transistor switching capacitor set comprises: a third transistor having a third gate, a third source and a third drain; a first capacitor having a first capacitor end connected with the first switching circuit node, and a second capacitor end connected with the third source and the first resistor end; a second capacitor having a third capacitor end connected with the third drain and the third resistor end, and a fourth capacitor end connected with the second switching circuit node; a first resistor having a first resistor end and a second resistor end; and a second resistor having a third resistor end and a fourth resistor end connected to the second resistor end, forming a first operating node. ### Claim 12 (depends on 11) The frequency synthesizer of claim 11, wherein the third gate and the first operating node are connected to a first operating voltage source for adjusting the operating status of the third transistor. ### Claim 13 (depends on 10) The frequency synthesizer of claim 10, wherein the second transistor switching capacitor set comprises: a fourth transistor having a fourth gate, a fourth source and a fourth drain; a third capacitor having a fifth capacitor end and a sixth capacitor end; a fourth capacitor having a seventh capacitor end and an eighth capacitor end; a third resistor having a fifth resistor end and a sixth resistor end; and a fourth resistor having a seventh resistor end and an eighth resistor end, wherein the fifth capacitor end is connected with the first switching circuit node, the sixth capacitor end is connected with the fourth source and the fifth resistor end, the seventh capacitor end is connected with the fourth drain and the seventh resistor end, the eighth capacitor end is connected with the second switching circuit node, and the sixth resistor end is connected to the eighth resistor end, forming a second operating node. ### Claim 14 (depends on 13) The frequency synthesizer of claim 13, wherein the fourth gate and the second operating node are connected to a second operating voltage source for adjusting the operating status of the fourth transistor. ### Claim 15 (depends on 10) The frequency synthesizer of claim 10, wherein the third transistor switching capacitor set comprises: a fifth transistor having a fifth gate, a fifth source and a fifth drain; a fifth capacitor having a ninth capacitor end and a tenth capacitor end; a sixth capacitor having an eleventh capacitor end and a twelfth capacitor end; a fifth resistor having a ninth resistor end and a tenth resistor end; and a sixth resistor having an eleventh resistor end and a twelfth resistor end, wherein the ninth capacitor end is connected with the first switching circuit node, the tenth capacitor end is connected with the fifth source and the ninth resistor end, the eleventh capacitor end is connected with the fifth drain and the eleventh resistor end, the twelfth capacitor end is connected with the second switching circuit node, and the tenth resistor end is connected to the twelfth resistor end, forming a third operating node. ### Claim 16 (depends on 15) The frequency synthesizer of claim 15, wherein the fifth gate and the third operating node are connected to a third operating voltage source for adjusting the operating status of the fifth transistor. ### Claim 17 (depends on 10) The frequency synthesizer of claim 10, wherein the first source and the second source are connected to a supply voltage source. ### Claim 18 (depends on 10) The frequency synthesizer of claim 10, wherein the VCO further comprises a blocking variable capacitor set connected in parallel to the parallel capacitor switching circuit, the blocking variable capacitor set fine tunes the operating frequency of the transistor VCO, and switches the parallel capacitor switching circuit to operate either in an accumulation mode or in a depletion mode. ### Claim 19 (depends on 10) The frequency synthesizer of claim 10, wherein the transistor VCO is a PMOS transistor VCO.