Data output controller
AssigneeHynix Semiconductor Inc.
InventorTae Jin Kang
Life of this patent
Estimating the term…
Abstract
Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.
Claims21
A data output controller comprising:
- a control signal generator configured to generate a control signal having a predetermined pulse width in response to a DQ off signal and a write signal;
- an enable signal generator configured to receive the control signal and a read signal and output a clock enable signal in synchronization with the control signal when the read signal is activated;
- and
- a clock generator configured to receive the clock enable signal and an internal clock signal, and generate a data clock signal in synchronization with the internal clock signal during an activation period of the clock enable signal,
- wherein the control signal generator includes:
- a first operation unit configured to perform a logical operation in response to a DQ off signal, a bank active signal and a write signal;
- a delay unit configured to output a delayed signal by delaying an output signal of the first operation unit;
- and
- a second operation unit configured to perform a logical operation with respect to the output signal of the first operation unit and the delayed signal of the delay unit.
A data output controller comprising:
- a control signal generator configured to generate a control signal having a predetermined pulse width in response to a DQ off signal and a write signal;
- an enable signal generator configured to receive the control signal and a read signal and output a clock enable signal in synchronization with the control signal when the read signal is activated;
- and
- a clock generator configured to receive the clock enable signal and an internal clock signal, and generate a data clock signal in synchronization with the internal clock signal during an activation period of the clock enable signal,
- wherein the control signal generator includes:
- a first operation unit configured to perform a logical operation in response to a DQ off signal, a bank active signal and a write signal;
- a delay unit configured to output a delayed signal by delaying an output signal of the first operation unit;
- and
- a second operation unit configured to perform a logical operation with respect to an inverse signal of the output signal of the first operation unit and an inverse signal of the delayed signal of the delay unit.
A data output controller comprising:
- a control signal generator, configured to receive a DQ off signal, a bank active signal and a write signal, generate a pulse signal in synchronization with the write signal and the DQ off signal and, output a control signal by delaying only a falling edge of the pulse signal by a predetermined interval when an external read command is applied;
- an enable signal generator configured to receive the control signal and a read signal and output an enable signal in synchronization with the control signal when the read signal is activated;
- and
- a clock generator configured to receive the enable signal and an internal clock signal and generate a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.
Dependencies are inferred from the claim text.