Delay locked loop circuit
AssigneeHynix Semiconductor Inc.
InventorKyung-Hoon Kim
Life of this patent
Estimating the term…
Abstract
A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.
Claims26
A delay locked loop, comprising;
- a clock delay compensation block configured to receive rising and falling clocks of an input clock and to generate a first multi clock and a second multi clock in response to the rising and falling clocks;
- a phase control block configured to receive the first multi clock and the second multi clock and to generate a phase control signal controlling a shifting operation based on the first multi clock and the second multi clock;
- and
- a multi-phase delay control block configured to perform the shifting operation to control the clock delay compensation block in response to the phase control signal,
- wherein the multi-phase delay control block includes:
- a switching unit for controlling a left-shift or right-shift operation in response to the phase control signal;
- a latching unit for latching an output of the switching unit;
- and
- a second logic combination unit for performing a logic operation on outputs of the switching unit to generate a delay control signal for controlling the clock delay compensation block.
A delay locked loop, comprising:
- a clock buffer configured to receive an input clock signal and to buffer the input clock signal to generate rising and falling clocks;
- a clock delay compensation block configured to receive the rising and falling clocks and to generate a first multi clock and a second multi clock in response to the rising and falling clocks received from the clock buffer;
- a phase control block configured to receive the first multi clock and the second multi clock and to generate a phase control signal controlling a shifting operation based on the first multi clock and the second multi clock;
- and
- a multi-phase delay control block configured to perform the shifting operation and to control the clock delay compensation block in response to the phase control signal,
- wherein the multi-phase delay control block further includes at least one bi-directional shift register.
Dependencies are inferred from the claim text.