Apparatus and method for generating a constant logical value in an integrated circuit
AssigneeAvago Technologies Enterprise IP (Singapore) Pte. Ltd.
InventorsRobert Harry Miller, Jr., Gilbert Yoh, Robert J. Martin
Life of this patent
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Abstract
An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.
Claims14
An apparatus for generating a constant logical value in an integrated circuit, comprising:
- a first logic network comprising first logical elements, each first logical element comprising at least one gate, no gates of the first logical elements being connected directly to a power supply, the first logic network having no logical input signals connected or provided thereto, the first logic network being configured to provide n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations;
- and
- a second logic network operably connected to the first logic network to receive the outputs therefrom and configured as a decoder to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.
A method for generating a constant logical value in an integrated circuit, comprising:
- generating n outputs having 2n possible output combinations using first logical elements disposed in a first logic network, each first logical element comprising at least one gate, no gates of the first logical elements being connected directly to a power supply, the first logic network having no logical input signals connected or provided thereto, where the n outputs assume a state that is a subset of the 2n possible output combinations;
- and
- decoding the n outputs to generate a constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.
Dependencies are inferred from the claim text.