Circuit for distributing an initial signal with a tree structure, protected against logic random events

A circuit, comprising:

• a first buffer having first and second input nodes and first and second output nodes, operable to receive first and second components of a first logic signal on its respective first and second input nodes, further operable to generate first and second components of a second logic signal on its respective first and second output nodes if the first and second components of said first logic signal are substantially similar, and still further operable to cause each of its first and second output nodes to take on a high-impedance state otherwise;
• and
• a second buffer having first and second input nodes respectively coupled to said first and second output nodes of the first buffer and further having a first output node, the second buffer being operable to receive the first and second components of said second logic signal on its respective first and second input nodes, further operable to generate a first component of a third logic signal on its first output node if the first and second components of said second logic signal are substantially similar, and to cause its first output node to take on a high-impedance state otherwise;
• wherein said second buffer comprises a second output node, and is further operable to generate a second component of said third logic signal on its second output node if the first and second components of said second logic signal are substantially similar, and to cause its second output node to take on a high-impedance state otherwise.

A system, comprising:

• an integrated circuit, comprising
• a first buffer having first and second input nodes and first and second output nodes, operable to receive first and second components of a first logic signal on said respective first and second input nodes of the first buffer, further operable to generate first and second components of a second logic signal on said respective first and second output nodes of the first buffer if the first and second components of said first logic signal are substantially similar, and still further operable to cause each of said first and second output nodes of the first buffer to take on a high-impedance state otherwise,
• a second buffer having first and second input nodes respectively coupled to said first and second output nodes of the first buffer and further having a first output node, the second buffer being operable to receive the first and second components of said second logic signal on its respective first and second input nodes, further operable to generate a first component of a third logic signal on its first output node if the first and second components of said second logic signal are substantially similar, and to cause its first output node to take on a high-impedance state otherwise,
• wherein said second buffer comprises a second output node, and is further operable to generate a second component of said third logic signal on its second output node if the first and second components of said second logic signal are substantially similar, and to cause its second output node to take on a high-impedance state otherwise;
• and
• a controller coupled to the integrated circuit.

A method, comprising:

• receiving first and second components of a first logic signal;
• generating first and second components of a second logic signal when the first and second components of said first logic signal are substantially identical, and driving first and second nodes to a high-impedance state otherwise;
• receiving said first and second components of the second logic signal;
• and
• generating first and second components of a third logic signal when the first and second components of the second logic signal are substantially identical, and driving third and fourth nodes to a high-impedance state otherwise.