Low amplitude differential output circuit and serial transmission interface using the same

A low amplitude differential output circuit comprising:

• a pre-buffer circuit configured to output a main buffer drive signal of a first drive signal and a second drive signal which are complimentary signals, as a differential signal;
• and
• a main buffer circuit connected with said pre-buffer circuit to output a differential output signal in response to said main buffer drive signal,
• wherein each of said first drive signal and said second drive signal has an amplitude between a first voltage and a second voltage,
• wherein said main buffer drive signal is outputted such that always one of said first and second drive signals is raised and then the other one of said first and second signals falls in amplitude, and
• wherein said pre-buffer output circuit comprises:
• a first CMOS inverter having a first MOS transistor and a second MOS transistor between said first voltage and said second voltage;
• and
• a second CMOS inverter having a third MOS transistor and a fourth MOS transistor between said first voltage and said second voltage,
• wherein said first CMOS inverter comprises a fifth MOS transistor between said first MOS transistor and said second MOS transistor,
• said second CMOS inverter comprises a sixth MOS transistor between said third MOS transistor of and said fourth MOS transistor,
• a first output terminal as a node between said first MOS transistor of and said fifth MOS transistor is connected with a gate of said sixth MOS transistor,
• a second output terminal as a node between said third MOS transistor of and said sixth MOS transistor is connected with a gate of said fifth MOS transistor,
• said first CMOS inverter outputs said second drive signal from said first output terminal in response to said first input signal, and
• said second CMOS inverter outputs said first drive signal from said second output terminal in response to said second input signal.

A low amplitude differential output circuit comprising:

• a pre-buffer circuit configured to output a main buffer drive signal of a first drive signal and a second drive signal which are complimentary signals, as a differential signal;
• and
• a main buffer circuit connected with said pre-buffer circuit to output a differential output signal in response to said main buffer drive signal,
• wherein each of said first drive signal and said second drive signal has an amplitude between a first voltage and a second voltage,
• wherein said main buffer drive signal is outputted such that one of said first and second drive signals is fallen and then with a predetermined delay the other one of said first and second drive signals is raised, and
• wherein said pre-buffer output circuit comprises:
• a first CMOS inverter having a first MOS transistor and a second MOS transistor between said first voltage and said second voltage;
• and
• a second CMOS inverter having a third MOS transistor and a fourth MOS transistor between said first voltage and said second voltage,
• wherein said first CMOS inverter comprises a fifth MOS transistor between said first MOS transistor and said second MOS transistor,
• said second CMOS inverter comprises a sixth MOS transistor between said third MOS transistor of and said fourth MOS transistor,
• a first output terminal as a node between said first MOS transistor of and said fifth MOS transistor is connected with a gate of said sixth MOS transistor,
• a second output terminal as a node between said third MOS transistor of and said sixth MOS transistor is connected with a gate of said fifth MOS transistor,
• said first CMOS inverter outputs said second drive signal from said first output terminal in response to said first input signal, and
• said second CMOS inverter outputs said first drive signal from said second output terminal in response to said second input signal.

A method of a low amplitude differential output circuit, comprising:

• receiving an input signal by a first circuit;
• converting the input signal to a first drive signal and a second drive signal which are complimentary signals by the first circuit, as a differential signal;
• delaying, by a predetermined period, one of the first and second drive signals from a rising time of the other one of the first and second drive signals;
• outputting a main buffer drive signal of the first drive signal and the second drive signal from the first circuit, as a differential signal, each of said first drive signal and said second drive signal has an amplitude between a first voltage and a second voltage, and the first drive signal and said second drive signal take a same voltage between said first voltage and a middle voltage between said first voltage and said second voltage;
• and
• outputting a differential output signal in response to the main buffer drive signal by a second circuit connected to the first circuit, said differential output signal including cross points adjacent to the middle voltage between a maximum level and a minimum level of the differential output signal.