Back to results
US 7,741,864 B2Granted
Fault tolerant asynchronous circuits
AssigneeAchronix Semiconductor Corporation
InventorsRajit Manohar, Clinton W. Kelly
Life of this patent
Estimating the term…
Abstract
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, such as the type introduced through radiation or, more broadly, single-event effects (SEEs). SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits, among others.
Claims32
A fault tolerant asynchronous circuit, comprising:
- a first logic circuit configured to receive a first input signal and generate a first output signal;
- a second logic circuit configured to receive a second input signal and generate a second output signal;
- and
- a keeper circuit including:
- first and second majority elements each connected to receive the first and second output signals from the first and second logic circuits, and
- third and fourth majority elements each connected through buffer circuits to an output of each of the first and second majority elements and to an output of each of the first and second logic circuits, each buffer circuit connecting a pair of the majority elements to physically space an input and output of the pair of the majority elements.
3 more elements
A method of fabricating a fault tolerant asynchronous circuit, comprising:
- fabricating a first logic circuit configured to receive a first input signal and generate a first output signal;
- fabricating a second logic circuit configured to receive a second input signal and generate a second output signal;
- and
- fabricating a keeper circuit, including:
- first and second majority elements each connected to receive the first and second output signals from the first and second logic circuits, and
- third and fourth majority elements each connected through buffer circuits to an output of each of the first and second majority elements and to an output of each of the first and second logic circuits, each buffer circuit connecting a pair of the majority elements to physically space an input and output of the pair of the majority elements.
3 more elements
A fault tolerant asynchronous circuit, comprising:
- a first logic circuit to receive an input signal and generate an output signal;
- a second logic circuit to receive the input signal and generate the output signal;
- a third logic circuit to receive the input signal and generate the output signal;
- and
- a fourth logic circuit to receive the input signal and generate the output signal;
- a first combining circuit to combine outputs of each of said first and second logic circuits to generate a first output signal;
- a second combining circuit to combine outputs of each of said third and fourth logic circuits to generate a second output signal;
- and
- a keeper circuit, including first and second majority elements each connected to receive the first and second output signals from the first and second combining circuits, and third and fourth majority elements each connected to an output of each of the first and second majority elements and to an output of each of the first and second combining circuits.
6 more elements
A keeper circuit comprising:
- a first circuit branch comprising a first majority element and a first pair of series-chain-connected buffer circuits connected to an output of the first majority element;
- a second circuit branch comprising a second majority element and a second pair of series-chain-connected buffer circuits connected to an output of the second majority element;
- and
- a third circuit branch comprising a third majority element and a third pair of series-chain-connected buffer circuits connected to an output of the third majority element, two inputs of the first majority element being connected to the second and third pairs of buffer circuits, two inputs of the second majority element being connected to the first and third pairs of buffer circuits, two inputs of the third majority element being connected to the first and second pairs of buffer circuits, the first and the third circuit branches to receive an input signal and a duplicate of the input signal, respectively, and to generate an output signal.
1 more element
Dependencies are inferred from the claim text.