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US 7,741,862 B2Granted
Semiconductor device including a signal generator activated upon occurring of a timing signal
AssigneeElpida Memory, Inc.
InventorYoshifumi Mochida
Life of this patent
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Abstract
A mode decode/latch circuit decodes an input signal based on a latch timing signal to output a test mode signal to a test execution circuit. Test mode signal line includes a high-resistance portion extending from the mode decode/latch circuit toward the vicinity of the test execution circuit and a low-resistance portion connecting together the distal end of the high-resistance portion and the input of the test execution circuit. A latch circuit for latching the test mode signal based on the latch timing signal is inserted in the low-resistance portion.
Claims7
A semiconductor device comprising:
- a signal generator for generating a specific signal at a timing specified by a timing signal;
- a signal receiving circuit for receiving said specific signal to execute a specific operation specified by said specific signal;
- a signal line for transferring said specific signal from said signal generator to said receiving circuit, said signal line including a first portion having a first end connected to said output of said signal generator and a second end, and a second portion having a resistance lower than a resistance of said first portion and connecting together said second end of said first portion and an input of said signal receiving circuit;
- and
- a latch circuit inserted in said second portion to latch said specific signal at a timing specified by said timing signal.
2 more elements
Dependencies are inferred from the claim text.