Integrated circuit bond pad structures

A bond pad structure formed on an integrated circuit that includes a plurality of metal interconnect layers, a plurality of via interconnect layers, a contact layer, and a polysilicon layer, comprising:

• bond pad metal in the shape of a bond pad located on top of an uppermost one of the metal interconnect layers;
• upper and lower dummy bond pads under the bond pad metal, wherein the upper dummy bond pad is in an uppermost one of the metal interconnect layers and is directly connected to the bond pad metal and wherein the lower dummy bond pad is located in an adjacent one of the metal interconnect layers;
• under the bond pad metal, at least four bond pad support structures in each of the metal interconnect layers not containing a dummy bond pad and in the polysilicon layer, wherein the bond pad support structures are under the bond pad metal, wherein the bond pad support structures are configured to define dielectric gaps in each of the metal interconnect layers;
• under the bond pad metal, vias in each of the via interconnect layers, wherein the vias connect the dummy bond pads to each other, connect the bond pad support structures under the lower dummy bond pad to the lower dummy bond pad, and connect the bond pad support structures in adjacent pairs of the metal interconnect layers to each other;
• metal plugs in the contact layer that connect the polysilicon bond pad support structures to respective ones of the bond pad support structures in a lowermost one of the metal interconnect layers;
• and
• under-pad circuitry located under the bond pad metal, wherein the under-pad circuitry includes interconnects and wherein some of the interconnects pass from under the bond pad metal to an area not under the bond pad metal through the dielectric gaps to connect the under-pad circuitry to circuitry on the integrated circuit that is not under the bond pad metal.

A bond pad structure on an integrated circuit having a substrate, a polysilicon layer on the substrate, a contact layer on the polysilicon layer, and a dielectric stack including a plurality of metal interconnect layers and a plurality of via interconnect layers, comprising:

• bond pad metal in the shape of a bond pad on top of the dielectric stack, wherein the bond pad metal has an area;
• bond pad support structures under the bond pad metal in at least a lowermost one of the metal interconnect layers and in the polysilicon layer, wherein the bond pad support structures in each layer comprise at least four square bond pad support structures each having an area less than one tenth of the bond pad area;
• a plurality of metal plugs in the contact layer under the bond pad metal that connect the bond pad support structures in the polysilicon layer to the bond pad support structures in the lowermost one of the metal interconnect layers, wherein the bond pad support structures in the lowermost metal interconnect layer are configured to define at least one dielectric gap in the lowermost metal interconnect layer;
• and
• under-pad circuitry located under the bond pad metal, wherein the under-pad circuitry includes interconnects in the metal interconnect layers and wherein at least one of the interconnects passes from under the bond pad metal to an area not under the bond pad metal through the dielectric gap to connect the under-pad circuitry to circuitry on the integrated circuit that is not under the bond pad metal.